What are the limiting factors for the bus speed on the S900? As we mentioned before, the XLR8 CarrierZIF board has a setting that will "request" 66MHz bus from the machine, so that and the variable bus speed implies a PLL clock. Is it just that the PLL in the S900 isn't up to generating that signal, or are there other components in the system that limit speed?
On another note, how is the PCI bus clock derived on the S900? -Drew B -- SuperMacs is sponsored by <http://lowendmac.com/> and... Small Dog Electronics http://www.smalldog.com | Refurbished Drives | Service & Replacement Parts [EMAIL PROTECTED] | & CDRWs on Sale! | Support Low End Mac <http://lowendmac.com/lists/support.html> SuperMacs list info: <http://lowendmac.com/supermacs/list.shtml> --> AOL users, remove "mailto:"; Send list messages to: <mailto:[EMAIL PROTECTED]> To unsubscribe, email: <mailto:[EMAIL PROTECTED]> For digest mode, email: <mailto:[EMAIL PROTECTED]> Subscription questions: <mailto:[EMAIL PROTECTED]> Archive: <http://www.mail-archive.com/supermacs%40mail.maclaunch.com/> --------------------------------------------------------------- >The Think Different Store http://www.ThinkDifferentStore.com ---------------------------------------------------------------
