On Sun, 21 Nov 1999 Constant Brouerius van Nidek <[EMAIL PROTECTED]> said:
> Some time ago somebody gave a description of the different card slots
> on the mainboard.
OK, you asked for it ...
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ISA (8-bit - The ORIGINAL IBM PC and XT bus)
Single section, single level edge connector, 31 "pins" per side, 62 total.
8-bit data bus. 20-bit address bus, thus 1Meg maximum addressable memory.
Originally spec'd at 4.77MHz by IBM, the ISA specified a maximum of 8MHz.
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ISA (16-bit - The IBM AT and later)
Double section, single level edge connector, w/36 added pins, 18 per side.
16-bit data bus. 20-bit address bus - Maximum 16Meg addressable memory.
Originally, the IBM AT had a 6MHz bus speed. Later systems ran at 8MHz.
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`--------------------' `---------------------------------' |
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EISA (32-bit - Extended Industry Standard Architecture. Not very popular.)
Double section, double level edge connector. Upper level was the same as 16-
bit ISA (AT), traces leading to lower level's pins were interdigitated
between the pins of the upper.
There were narrow slots cut in the lower level of the card edge. These slots
correspond to bars that blocked the lower half of the socket, and prevented
a standard ISA card edge from making contact with anything but the upper
level connections. You could safely use any ISA card, 8- or 16-bit, in an
EISA slot.
32-bit data bus. 32-bit address bus, 4Gig maximum addressable memory space.
Not sure, don't have the EISA spec handy, but I _THINK_ 8MHz max bus speed.
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| HHHHHHHHHHHHHHHHHH | | HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH | |
| UUUUUUUUU UUUUUUUU | | UUUUUU UUUUUUUUUUUUU UUUUUUUUUU | |
`---------- ---------' `------- ------------- -----------' |
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(An enlarged example of the interdigitated contacts)
|XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| | / Upper
|XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| | / Level
|XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| | \ Contacts
|XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| | \ (ISA)
|XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| H |XXXXX| |
__ __H__ __H__ __H__ __H__ __H__ |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
XX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |XXXXX| |
___________________________________________________________/
Since the EISA design required closer tolerances and an expensive socket,
not to mention a special chip-set on every I/O card to allow them to auto-
configure (a predecessor of Plug-n-Play), EISA cost more to implement.
Most EISA-bus motherboards ended up in network server systems, since their
moderately fast throughput and large number of bus slots (some had as many
as 14 slots) allowed them to handle greater numbers of disk controllers,
network interface cards (NICs), and multi-port serial interface cards.
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VLB was the preferred high-speed bus for the 486.
VLB (32-bit - VESA [Video Electronics Standards Association] Local Bus)
Four section, single level edge connector, it added 112 pins to the ISA-16.
32-Bit data bus. 32-bit address bus - Maximum 4Gig addressable memory.
The 2 added card edge sections run at the CPU clock speed, up to 33MHz.
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The pins on the 2 added card edge sections are much closer together than
those on the ISA-16 sections.
Intel _was_ a member of VESA, and as such had a hand in defining the VLB's
design architecture. Such decisions as using lightly- or non-buffered CPU
signals on the VLB connectors, thus limiting the motherboards to no more
than 2 or 3 VLB sockets, have been attributed to Intel. This is untrue, as
Intel was only one among many processor, chip set, motherboard, and I/O card
companies with representatives in VESA.
What _IS_ true is that, shortly before the first VLB systems appeared, Intel
left VESA, and shortly thereafter introduced the PCI bus, which IS buffered;
and indeed is optimized for use with Pentium-class CPUs, since it is
designed with FIFO (First-In, First-Out) buffering to allow burst-mode
operation.
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PCI _WAS_ used in a few 486 designs, but was intended and optimized for the
Pentium.
PCI (32- or 64-bit - Peripheral Connect Interface)
The number of pins is dependent upon which version of the PCI standard, 32-
or 64-bit, is used on the card. 32- or 64-bit data bus, 32-bit address bus.
Maximum addressable memory is 4Gig. Bus speed is 33 or 66MHz, depending upon
the PCI version.
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The PCI bus design has also been used with PowerPC-based systems, notably
the Apple Macintosh.
Hope this is what you were looking for.
Later,
Dave
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