Author: manu
Date: Mon Oct 2 15:48:39 2017
New Revision: 324208
URL: https://svnweb.freebsd.org/changeset/base/324208
Log:
Allwinner H3 ccu: Use clock/reset IDs from dt-bindings
Do not redefines resets and clocks ID which are already in the
dt-bindings include directory. Those files are under dual licence
GPL2/MIT so use them directly.
Modified:
head/sys/arm/allwinner/clkng/ccu_h3.c
head/sys/arm/allwinner/clkng/ccu_h3.h
Modified: head/sys/arm/allwinner/clkng/ccu_h3.c
==============================================================================
--- head/sys/arm/allwinner/clkng/ccu_h3.c Mon Oct 2 14:22:35 2017
(r324207)
+++ head/sys/arm/allwinner/clkng/ccu_h3.c Mon Oct 2 15:48:39 2017
(r324208)
@@ -43,157 +43,198 @@ __FBSDID("$FreeBSD$");
#include <arm/allwinner/clkng/aw_clk_nkmp.h>
#include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
#include "ccu_h3.h"
+/* Non-exported resets */
+#define RST_BUS_SCR 53
+
+/* Non-exported clocks */
+#define CLK_PLL_CPUX 0
+#define CLK_PLL_AUDIO_BASE 1
+#define CLK_PLL_AUDIO 2
+#define CLK_PLL_AUDIO_2X 3
+#define CLK_PLL_AUDIO_4X 4
+#define CLK_PLL_AUDIO_8X 5
+#define CLK_PLL_VIDEO 6
+#define CLK_PLL_VE 7
+#define CLK_PLL_DDR 8
+#define CLK_PLL_PERIPH0_2X 10
+#define CLK_PLL_GPU 11
+#define CLK_PLL_PERIPH1 12
+#define CLK_PLL_DE 13
+
+#define CLK_AXI 15
+#define CLK_AHB1 16
+#define CLK_APB1 17
+#define CLK_APB2 18
+#define CLK_AHB2 19
+
+#define CLK_BUS_SCR 66
+
+#define CLK_USBPHY0 88
+#define CLK_USBPHY1 89
+#define CLK_USBPHY2 90
+#define CLK_USBPHY3 91
+#define CLK_USBOHCI0 92
+#define CLK_USBOHCI1 93
+#define CLK_USBOHCI2 94
+#define CLK_USBOHCI3 95
+#define CLK_DRAM 96
+
+#define CLK_MBUS 113
+
static struct aw_ccung_reset h3_ccu_resets[] = {
- CCU_RESET(H3_RST_USB_PHY0, 0xcc, 0)
- CCU_RESET(H3_RST_USB_PHY1, 0xcc, 1)
- CCU_RESET(H3_RST_USB_PHY2, 0xcc, 2)
- CCU_RESET(H3_RST_USB_PHY3, 0xcc, 3)
+ CCU_RESET(RST_USB_PHY0, 0xcc, 0)
+ CCU_RESET(RST_USB_PHY1, 0xcc, 1)
+ CCU_RESET(RST_USB_PHY2, 0xcc, 2)
+ CCU_RESET(RST_USB_PHY3, 0xcc, 3)
- CCU_RESET(H3_RST_MBUS, 0xfc, 31)
+ CCU_RESET(RST_MBUS, 0xfc, 31)
- CCU_RESET(H3_RST_BUS_CE, 0x2c0, 5)
- CCU_RESET(H3_RST_BUS_DMA, 0x2c0, 6)
- CCU_RESET(H3_RST_BUS_MMC0, 0x2c0, 8)
- CCU_RESET(H3_RST_BUS_MMC1, 0x2c0, 9)
- CCU_RESET(H3_RST_BUS_MMC2, 0x2c0, 10)
- CCU_RESET(H3_RST_BUS_NAND, 0x2c0, 13)
- CCU_RESET(H3_RST_BUS_DRAM, 0x2c0, 14)
- CCU_RESET(H3_RST_BUS_EMAC, 0x2c0, 17)
- CCU_RESET(H3_RST_BUS_TS, 0x2c0, 18)
- CCU_RESET(H3_RST_BUS_HSTIMER, 0x2c0, 19)
- CCU_RESET(H3_RST_BUS_SPI0, 0x2c0, 20)
- CCU_RESET(H3_RST_BUS_SPI1, 0x2c0, 21)
- CCU_RESET(H3_RST_BUS_OTG, 0x2c0, 23)
- CCU_RESET(H3_RST_BUS_EHCI0, 0x2c0, 24)
- CCU_RESET(H3_RST_BUS_EHCI1, 0x2c0, 25)
- CCU_RESET(H3_RST_BUS_EHCI2, 0x2c0, 26)
- CCU_RESET(H3_RST_BUS_EHCI3, 0x2c0, 27)
- CCU_RESET(H3_RST_BUS_OHCI0, 0x2c0, 28)
- CCU_RESET(H3_RST_BUS_OHCI1, 0x2c0, 29)
- CCU_RESET(H3_RST_BUS_OHCI2, 0x2c0, 30)
- CCU_RESET(H3_RST_BUS_OHCI3, 0x2c0, 31)
+ CCU_RESET(RST_BUS_CE, 0x2c0, 5)
+ CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
+ CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
+ CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
+ CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
+ CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
+ CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
+ CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
+ CCU_RESET(RST_BUS_TS, 0x2c0, 18)
+ CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
+ CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
+ CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
+ CCU_RESET(RST_BUS_OTG, 0x2c0, 23)
+ CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24)
+ CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25)
+ CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26)
+ CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27)
+ CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28)
+ CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29)
+ CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30)
+ CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31)
- CCU_RESET(H3_RST_BUS_VE, 0x2c4, 0)
- CCU_RESET(H3_RST_BUS_TCON0, 0x2c4, 3)
- CCU_RESET(H3_RST_BUS_TCON1, 0x2c4, 4)
- CCU_RESET(H3_RST_BUS_DEINTERLACE, 0x2c4, 5)
- CCU_RESET(H3_RST_BUS_CSI, 0x2c4, 8)
- CCU_RESET(H3_RST_BUS_TVE, 0x2c4, 9)
- CCU_RESET(H3_RST_BUS_HDMI0, 0x2c4, 10)
- CCU_RESET(H3_RST_BUS_HDMI1, 0x2c4, 11)
- CCU_RESET(H3_RST_BUS_DE, 0x2c4, 12)
- CCU_RESET(H3_RST_BUS_GPU, 0x2c4, 20)
- CCU_RESET(H3_RST_BUS_MSGBOX, 0x2c4, 21)
- CCU_RESET(H3_RST_BUS_SPINLOCK, 0x2c4, 22)
- CCU_RESET(H3_RST_BUS_DBG, 0x2c4, 31)
+ CCU_RESET(RST_BUS_VE, 0x2c4, 0)
+ CCU_RESET(RST_BUS_TCON0, 0x2c4, 3)
+ CCU_RESET(RST_BUS_TCON1, 0x2c4, 4)
+ CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5)
+ CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
+ CCU_RESET(RST_BUS_TVE, 0x2c4, 9)
+ CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
+ CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
+ CCU_RESET(RST_BUS_DE, 0x2c4, 12)
+ CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
+ CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
+ CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
+ CCU_RESET(RST_BUS_DBG, 0x2c4, 31)
- CCU_RESET(H3_RST_BUS_EPHY, 0x2c8, 2)
+ CCU_RESET(RST_BUS_EPHY, 0x2c8, 2)
- CCU_RESET(H3_RST_BUS_CODEC, 0x2d0, 0)
- CCU_RESET(H3_RST_BUS_SPDIF, 0x2d0, 1)
- CCU_RESET(H3_RST_BUS_THS, 0x2d0, 8)
- CCU_RESET(H3_RST_BUS_I2S0, 0x2d0, 12)
- CCU_RESET(H3_RST_BUS_I2S1, 0x2d0, 13)
- CCU_RESET(H3_RST_BUS_I2S2, 0x2d0, 14)
+ CCU_RESET(RST_BUS_CODEC, 0x2d0, 0)
+ CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
+ CCU_RESET(RST_BUS_THS, 0x2d0, 8)
+ CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
+ CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
+ CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
- CCU_RESET(H3_RST_BUS_I2C0, 0x2d8, 0)
- CCU_RESET(H3_RST_BUS_I2C1, 0x2d8, 1)
- CCU_RESET(H3_RST_BUS_I2C2, 0x2d8, 2)
- CCU_RESET(H3_RST_BUS_UART0, 0x2d8, 16)
- CCU_RESET(H3_RST_BUS_UART1, 0x2d8, 17)
- CCU_RESET(H3_RST_BUS_UART2, 0x2d8, 18)
- CCU_RESET(H3_RST_BUS_UART3, 0x2d8, 19)
- CCU_RESET(H3_RST_BUS_SCR, 0x2d8, 20)
+ CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
+ CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
+ CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
+ CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
+ CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
+ CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
+ CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
+ CCU_RESET(RST_BUS_SCR, 0x2d8, 20)
};
static struct aw_ccung_gate h3_ccu_gates[] = {
- CCU_GATE(H3_CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
- CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
- CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
- CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
- CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
- CCU_GATE(H3_CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
- CCU_GATE(H3_CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
- CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17)
- CCU_GATE(H3_CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
- CCU_GATE(H3_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
- CCU_GATE(H3_CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
- CCU_GATE(H3_CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
- CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
- CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
- CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
- CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26)
- CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27)
- CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
- CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
- CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30)
- CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31)
+ CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
+ CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
+ CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
+ CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
+ CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
+ CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
+ CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
+ CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17)
+ CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
+ CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
+ CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
+ CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
+ CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
+ CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
+ CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
+ CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26)
+ CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27)
+ CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
+ CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
+ CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30)
+ CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31)
- CCU_GATE(H3_CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
- CCU_GATE(H3_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
- CCU_GATE(H3_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
- CCU_GATE(H3_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
- CCU_GATE(H3_CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
- CCU_GATE(H3_CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9)
- CCU_GATE(H3_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
- CCU_GATE(H3_CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
- CCU_GATE(H3_CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
- CCU_GATE(H3_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
- CCU_GATE(H3_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
+ CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
+ CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
+ CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
+ CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
+ CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
+ CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9)
+ CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
+ CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
+ CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
+ CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
+ CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
- CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
- CCU_GATE(H3_CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
- CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
- CCU_GATE(H3_CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
- CCU_GATE(H3_CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
- CCU_GATE(H3_CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
- CCU_GATE(H3_CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
+ CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
+ CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
+ CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
+ CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
+ CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
+ CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
+ CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
- CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
- CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
- CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
- CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
- CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
- CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
- CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
- CCU_GATE(H3_CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20)
+ CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
+ CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
+ CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
+ CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
+ CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
+ CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
+ CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
+ CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20)
- CCU_GATE(H3_CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0)
- CCU_GATE(H3_CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
+ CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0)
+ CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
- CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8)
- CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9)
- CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10)
- CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11)
- CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16)
- CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17)
- CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18)
- CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19)
+ CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8)
+ CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9)
+ CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10)
+ CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11)
+ CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16)
+ CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17)
+ CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18)
+ CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19)
- CCU_GATE(H3_CLK_THS, "ths", "thsdiv", 0x74, 31)
- CCU_GATE(H3_CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31)
- CCU_GATE(H3_CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
- CCU_GATE(H3_CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
+ CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31)
+ CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31)
+ CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
+ CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
- CCU_GATE(H3_CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
- CCU_GATE(H3_CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
- CCU_GATE(H3_CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
- CCU_GATE(H3_CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
+ CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
+ CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
+ CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
+ CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
- CCU_GATE(H3_CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
+ CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
- CCU_GATE(H3_CLK_AVS, "avs", "osc24M", 0x144, 31)
+ CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
- CCU_GATE(H3_CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
+ CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
- CCU_GATE(H3_CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
+ CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
};
static const char *pll_cpux_parents[] = {"osc24M"};
NKMP_CLK(pll_cpux_clk,
- H3_CLK_PLL_CPUX, /* id */
+ CLK_PLL_CPUX, /* id */
"pll_cpux", pll_cpux_parents, /* name, parents */
0x00, /* offset */
8, 5, 0, 0, /* n factor */
@@ -206,7 +247,7 @@ NKMP_CLK(pll_cpux_clk,
static const char *pll_audio_parents[] = {"osc24M"};
NKMP_CLK(pll_audio_clk,
- H3_CLK_PLL_AUDIO, /* id */
+ CLK_PLL_AUDIO, /* id */
"pll_audio", pll_audio_parents, /* name, parents */
0x08, /* offset */
8, 7, 0, 0, /* n factor */
@@ -219,7 +260,7 @@ NKMP_CLK(pll_audio_clk,
static const char *pll_audio_mult_parents[] = {"pll_audio"};
FIXED_CLK(pll_audio_2x_clk,
- H3_CLK_PLL_AUDIO_2X, /* id */
+ CLK_PLL_AUDIO_2X, /* id */
"pll_audio-2x", /* name */
pll_audio_mult_parents, /* parent */
0, /* freq */
@@ -227,7 +268,7 @@ FIXED_CLK(pll_audio_2x_clk,
1, /* div */
0); /* flags */
FIXED_CLK(pll_audio_4x_clk,
- H3_CLK_PLL_AUDIO_4X, /* id */
+ CLK_PLL_AUDIO_4X, /* id */
"pll_audio-4x", /* name */
pll_audio_mult_parents, /* parent */
0, /* freq */
@@ -235,7 +276,7 @@ FIXED_CLK(pll_audio_4x_clk,
1, /* div */
0); /* flags */
FIXED_CLK(pll_audio_8x_clk,
- H3_CLK_PLL_AUDIO_8X, /* id */
+ CLK_PLL_AUDIO_8X, /* id */
"pll_audio-8x", /* name */
pll_audio_mult_parents, /* parent */
0, /* freq */
@@ -245,7 +286,7 @@ FIXED_CLK(pll_audio_8x_clk,
static const char *pll_video_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_video_clk,
- H3_CLK_PLL_VIDEO, /* id */
+ CLK_PLL_VIDEO, /* id */
"pll_video", pll_video_parents, /* name, parents */
0x10, /* offset */
8, 7, 0, 0, /* n factor */
@@ -257,7 +298,7 @@ NM_CLK_WITH_FRAC(pll_video_clk,
static const char *pll_ve_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_ve_clk,
- H3_CLK_PLL_VE, /* id */
+ CLK_PLL_VE, /* id */
"pll_ve", pll_ve_parents, /* name, parents */
0x18, /* offset */
8, 7, 0, 0, /* n factor */
@@ -269,7 +310,7 @@ NM_CLK_WITH_FRAC(pll_ve_clk,
static const char *pll_ddr_parents[] = {"osc24M"};
NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
- H3_CLK_PLL_DDR, /* id */
+ CLK_PLL_DDR, /* id */
"pll_ddr", pll_ddr_parents, /* name, parents */
0x20, /* offset */
8, 5, 0, 0, /* n factor */
@@ -284,7 +325,7 @@ NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
static const char *pll_periph0_parents[] = {"osc24M"};
static const char *pll_periph0_2x_parents[] = {"pll_periph0"};
NKMP_CLK(pll_periph0_clk,
- H3_CLK_PLL_PERIPH0, /* id */
+ CLK_PLL_PERIPH0, /* id */
"pll_periph0", pll_periph0_parents, /* name, parents */
0x28, /* offset */
8, 5, 0, 0, /* n factor */
@@ -295,7 +336,7 @@ NKMP_CLK(pll_periph0_clk,
28, 1000, /* lock */
AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
FIXED_CLK(pll_periph0_2x_clk,
- H3_CLK_PLL_PERIPH0_2X, /* id */
+ CLK_PLL_PERIPH0_2X, /* id */
"pll_periph0-2x", /* name */
pll_periph0_2x_parents, /* parent */
0, /* freq */
@@ -305,7 +346,7 @@ FIXED_CLK(pll_periph0_2x_clk,
static const char *pll_gpu_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_gpu_clk,
- H3_CLK_PLL_GPU, /* id */
+ CLK_PLL_GPU, /* id */
"pll_gpu", pll_gpu_parents, /* name, parents */
0x38, /* offset */
8, 7, 0, 0, /* n factor */
@@ -317,7 +358,7 @@ NM_CLK_WITH_FRAC(pll_gpu_clk,
static const char *pll_periph1_parents[] = {"osc24M"};
NKMP_CLK(pll_periph1_clk,
- H3_CLK_PLL_PERIPH1, /* id */
+ CLK_PLL_PERIPH1, /* id */
"pll_periph1", pll_periph1_parents, /* name, parents */
0x44, /* offset */
8, 5, 0, 0, /* n factor */
@@ -330,7 +371,7 @@ NKMP_CLK(pll_periph1_clk,
static const char *pll_de_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_de_clk,
- H3_CLK_PLL_DE, /* id */
+ CLK_PLL_DE, /* id */
"pll_de", pll_de_parents, /* name, parents */
0x48, /* offset */
8, 7, 0, 0, /* n factor */
@@ -342,20 +383,20 @@ NM_CLK_WITH_FRAC(pll_de_clk,
static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux",
"pll_cpux"};
MUX_CLK(cpux_clk,
- H3_CLK_CPUX, /* id */
+ CLK_CPUX, /* id */
"cpux", cpux_parents, /* name, parents */
0x50, 16, 2); /* offset, shift, width */
static const char *axi_parents[] = {"cpux"};
DIV_CLK(axi_clk,
- H3_CLK_AXI, /* id */
+ CLK_AXI, /* id */
"axi", axi_parents, /* name, parents */
0x50, /* offset */
0, 2, /* shift, width */
0, NULL); /* flags, div table */
static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
-PREDIV_CLK(ahb1_clk, H3_CLK_AHB1, /* id */
+PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */
"ahb1", ahb1_parents, /* name,
parents */
0x54, /* offset */
12, 2, /* mux */
@@ -372,7 +413,7 @@ static struct clk_div_table apb1_div_table[] = {
{ },
};
DIV_CLK(apb1_clk,
- H3_CLK_APB1, /* id */
+ CLK_APB1, /* id */
"apb1", apb1_parents, /* name, parents */
0x54, /* offset */
8, 2, /* shift, width */
@@ -381,7 +422,7 @@ DIV_CLK(apb1_clk,
static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0",
"pll_periph0"};
NM_CLK(apb2_clk,
- H3_CLK_APB2, /* id */
+ CLK_APB2, /* id */
"apb2", apb2_parents, /* name, parents */
0x58, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
@@ -391,7 +432,7 @@ NM_CLK(apb2_clk,
AW_CLK_HAS_MUX);
static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
-PREDIV_CLK(ahb2_clk, H3_CLK_AHB2, /* id */
+PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */
"ahb2", ahb2_parents, /* name,
parents */
0x5c, /* offset */
0, 2, /* mux */
@@ -408,7 +449,7 @@ static struct clk_div_table ths_div_table[] = {
{ },
};
DIV_CLK(thsdiv_clk,
- 0, /* id */
+ 0, /* id */
"thsdiv", ths_parents, /* name, parents */
0x74, /* offset */
0, 2, /* shift, width */
@@ -417,7 +458,7 @@ DIV_CLK(thsdiv_clk,
static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"};
NM_CLK(nand_clk,
- H3_CLK_NAND, "nand", mod_parents, /* id, name, parents */
+ CLK_NAND, "nand", mod_parents, /* id, name, parents */
0x80, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -426,7 +467,7 @@ NM_CLK(nand_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
NM_CLK(mmc0_clk,
- H3_CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
+ CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
0x88, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -436,7 +477,7 @@ NM_CLK(mmc0_clk,
AW_CLK_REPARENT); /* flags */
NM_CLK(mmc1_clk,
- H3_CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
+ CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
0x8c, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -446,7 +487,7 @@ NM_CLK(mmc1_clk,
AW_CLK_REPARENT); /* flags */
NM_CLK(mmc2_clk,
- H3_CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
+ CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
0x90, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -457,7 +498,7 @@ NM_CLK(mmc2_clk,
static const char *ts_parents[] = {"osc24M", "pll_periph0"};
NM_CLK(ts_clk,
- H3_CLK_TS, "ts", ts_parents, /* id, name, parents */
+ CLK_TS, "ts", ts_parents, /* id, name, parents */
0x98, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -466,7 +507,7 @@ NM_CLK(ts_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
NM_CLK(ce_clk,
- H3_CLK_CE, "ce", mod_parents, /* id, name, parents */
+ CLK_CE, "ce", mod_parents, /* id, name, parents */
0x9C, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -475,7 +516,7 @@ NM_CLK(ce_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
NM_CLK(spi0_clk,
- H3_CLK_SPI0, "spi0", mod_parents, /* id, name, parents */
+ CLK_SPI0, "spi0", mod_parents, /* id, name, parents */
0xA0, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -485,7 +526,7 @@ NM_CLK(spi0_clk,
AW_CLK_REPARENT); /* flags */
NM_CLK(spi1_clk,
- H3_CLK_SPI1, "spi1", mod_parents, /* id, name, parents */
+ CLK_SPI1, "spi1", mod_parents, /* id, name, parents */
0xA4, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -507,7 +548,7 @@ MUX_CLK(i2s2mux_clk,
static const char *spdif_parents[] = {"pll_audio"};
NM_CLK(spdif_clk,
- H3_CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */
+ CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */
0xC0, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */
0, 4, 0, 0, /* m factor */
@@ -517,7 +558,7 @@ NM_CLK(spdif_clk,
static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"};
NM_CLK(dram_clk,
- H3_CLK_DRAM, "dram", dram_parents, /* id, name, parents */
+ CLK_DRAM, "dram", dram_parents, /* id, name, parents */
0xF4, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -527,7 +568,7 @@ NM_CLK(dram_clk,
static const char *de_parents[] = {"pll_periph0-2x", "pll_de"};
NM_CLK(de_clk,
- H3_CLK_DE, "de", de_parents, /* id, name, parents */
+ CLK_DE, "de", de_parents, /* id, name, parents */
0x104, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -537,7 +578,7 @@ NM_CLK(de_clk,
static const char *tcon0_parents[] = {"pll_video"};
NM_CLK(tcon0_clk,
- H3_CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */
+ CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */
0x118, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -547,7 +588,7 @@ NM_CLK(tcon0_clk,
static const char *tve_parents[] = {"pll_de", "pll_periph1"};
NM_CLK(tve_clk,
- H3_CLK_TVE, "tve", tve_parents, /* id, name, parents */
+ CLK_TVE, "tve", tve_parents, /* id, name, parents */
0x120, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -557,7 +598,7 @@ NM_CLK(tve_clk,
static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
NM_CLK(deinterlace_clk,
- H3_CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name,
parents */
+ CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name,
parents */
0x124, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -567,7 +608,7 @@ NM_CLK(deinterlace_clk,
static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
NM_CLK(csi_sclk_clk,
- H3_CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
+ CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
0x134, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
16, 4, 0, 0, /* m factor */
@@ -577,7 +618,7 @@ NM_CLK(csi_sclk_clk,
static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"};
NM_CLK(csi_mclk_clk,
- H3_CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
+ CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
0x134, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -587,7 +628,7 @@ NM_CLK(csi_mclk_clk,
static const char *ve_parents[] = {"pll_ve"};
NM_CLK(ve_clk,
- H3_CLK_VE, "ve", ve_parents, /* id, name, parents */
+ CLK_VE, "ve", ve_parents, /* id, name, parents */
0x13C, /* offset */
16, 3, 0, 0, /* n factor */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
@@ -597,7 +638,7 @@ NM_CLK(ve_clk,
static const char *hdmi_parents[] = {"pll_video"};
NM_CLK(hdmi_clk,
- H3_CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
+ CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
0x150, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -607,7 +648,7 @@ NM_CLK(hdmi_clk,
static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"};
NM_CLK(mbus_clk,
- H3_CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
+ CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
0x15C, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 3, 0, 0, /* m factor */
@@ -617,7 +658,7 @@ NM_CLK(mbus_clk,
static const char *gpu_parents[] = {"pll_gpu"};
NM_CLK(gpu_clk,
- H3_CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
+ CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
0x1A0, /* offset */
0, 2, 0, 0, /* n factor */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
Modified: head/sys/arm/allwinner/clkng/ccu_h3.h
==============================================================================
--- head/sys/arm/allwinner/clkng/ccu_h3.h Mon Oct 2 14:22:35 2017
(r324207)
+++ head/sys/arm/allwinner/clkng/ccu_h3.h Mon Oct 2 15:48:39 2017
(r324208)
@@ -29,177 +29,6 @@
#ifndef __CCU_H3_H__
#define __CCU_H3_H__
-#define H3_RST_USB_PHY0 0
-#define H3_RST_USB_PHY1 1
-#define H3_RST_USB_PHY2 2
-#define H3_RST_USB_PHY3 3
-#define H3_RST_MBUS 4
-#define H3_RST_BUS_CE 5
-#define H3_RST_BUS_DMA 6
-#define H3_RST_BUS_MMC0 7
-#define H3_RST_BUS_MMC1 8
-#define H3_RST_BUS_MMC2 9
-#define H3_RST_BUS_NAND 10
-#define H3_RST_BUS_DRAM 11
-#define H3_RST_BUS_EMAC 12
-#define H3_RST_BUS_TS 13
-#define H3_RST_BUS_HSTIMER 14
-#define H3_RST_BUS_SPI0 15
-#define H3_RST_BUS_SPI1 16
-#define H3_RST_BUS_OTG 17
-#define H3_RST_BUS_EHCI0 18
-#define H3_RST_BUS_EHCI1 19
-#define H3_RST_BUS_EHCI2 20
-#define H3_RST_BUS_EHCI3 21
-#define H3_RST_BUS_OHCI0 22
-#define H3_RST_BUS_OHCI1 23
-#define H3_RST_BUS_OHCI2 24
-#define H3_RST_BUS_OHCI3 25
-#define H3_RST_BUS_VE 26
-#define H3_RST_BUS_TCON0 27
-#define H3_RST_BUS_TCON1 28
-#define H3_RST_BUS_DEINTERLACE 29
-#define H3_RST_BUS_CSI 30
-#define H3_RST_BUS_TVE 31
-#define H3_RST_BUS_HDMI0 32
-#define H3_RST_BUS_HDMI1 33
-#define H3_RST_BUS_DE 34
-#define H3_RST_BUS_GPU 35
-#define H3_RST_BUS_MSGBOX 36
-#define H3_RST_BUS_SPINLOCK 37
-#define H3_RST_BUS_DBG 38
-#define H3_RST_BUS_EPHY 39
-#define H3_RST_BUS_CODEC 40
-#define H3_RST_BUS_SPDIF 41
-#define H3_RST_BUS_THS 42
-#define H3_RST_BUS_I2S0 43
-#define H3_RST_BUS_I2S1 44
-#define H3_RST_BUS_I2S2 45
-#define H3_RST_BUS_I2C0 46
-#define H3_RST_BUS_I2C1 47
-#define H3_RST_BUS_I2C2 48
-#define H3_RST_BUS_UART0 49
-#define H3_RST_BUS_UART1 50
-#define H3_RST_BUS_UART2 51
-#define H3_RST_BUS_UART3 52
-#define H3_RST_BUS_SCR 53
-
-#define H3_CLK_PLL_CPUX 0
-#define H3_CLK_PLL_AUDIO_BASE 1
-#define H3_CLK_PLL_AUDIO 2
-#define H3_CLK_PLL_AUDIO_2X 3
-#define H3_CLK_PLL_AUDIO_4X 4
-#define H3_CLK_PLL_AUDIO_8X 5
-#define H3_CLK_PLL_VIDEO 6
-#define H3_CLK_PLL_VE 7
-#define H3_CLK_PLL_DDR 8
-#define H3_CLK_PLL_PERIPH0 9
-#define H3_CLK_PLL_PERIPH0_2X 10
-#define H3_CLK_PLL_GPU 11
-#define H3_CLK_PLL_PERIPH1 12
-#define H3_CLK_PLL_DE 13
-#define H3_CLK_CPUX 14
-#define H3_CLK_AXI 15
-#define H3_CLK_AHB1 16
-#define H3_CLK_APB1 17
-#define H3_CLK_APB2 18
-#define H3_CLK_AHB2 19
-#define H3_CLK_BUS_CE 20
-#define H3_CLK_BUS_DMA 21
-#define H3_CLK_BUS_MMC0 22
-#define H3_CLK_BUS_MMC1 23
-#define H3_CLK_BUS_MMC2 24
-#define H3_CLK_BUS_NAND 25
-#define H3_CLK_BUS_DRAM 26
-#define H3_CLK_BUS_EMAC 27
-#define H3_CLK_BUS_TS 28
-#define H3_CLK_BUS_HSTIMER 29
-#define H3_CLK_BUS_SPI0 30
-#define H3_CLK_BUS_SPI1 31
-#define H3_CLK_BUS_OTG 32
-#define H3_CLK_BUS_EHCI0 33
-#define H3_CLK_BUS_EHCI1 34
-#define H3_CLK_BUS_EHCI2 35
-#define H3_CLK_BUS_EHCI3 36
-#define H3_CLK_BUS_OHCI0 37
-#define H3_CLK_BUS_OHCI1 38
-#define H3_CLK_BUS_OHCI2 39
-#define H3_CLK_BUS_OHCI3 40
-#define H3_CLK_BUS_VE 41
-#define H3_CLK_BUS_TCON0 42
-#define H3_CLK_BUS_TCON1 43
-#define H3_CLK_BUS_DEINTERLACE 44
-#define H3_CLK_BUS_CSI 45
-#define H3_CLK_BUS_TVE 46
-#define H3_CLK_BUS_HDMI 47
-#define H3_CLK_BUS_DE 48
-#define H3_CLK_BUS_GPU 49
-#define H3_CLK_BUS_MSGBOX 50
-#define H3_CLK_BUS_SPINLOCK 51
-#define H3_CLK_BUS_CODEC 52
-#define H3_CLK_BUS_SPDIF 53
-#define H3_CLK_BUS_PIO 54
-#define H3_CLK_BUS_THS 55
-#define H3_CLK_BUS_I2S0 56
-#define H3_CLK_BUS_I2S1 57
-#define H3_CLK_BUS_I2S2 58
-#define H3_CLK_BUS_I2C0 59
-#define H3_CLK_BUS_I2C1 60
-#define H3_CLK_BUS_I2C2 61
-#define H3_CLK_BUS_UART0 62
-#define H3_CLK_BUS_UART1 63
-#define H3_CLK_BUS_UART2 64
-#define H3_CLK_BUS_UART3 65
-#define H3_CLK_BUS_SCR 66
-#define H3_CLK_BUS_EPHY 67
-#define H3_CLK_BUS_DBG 68
-#define H3_CLK_THS 69
-#define H3_CLK_NAND 70
-#define H3_CLK_MMC0 71
-#define H3_CLK_MMC0_SAMPLE 72
-#define H3_CLK_MMC0_OUTPUT 73
-#define H3_CLK_MMC1 74
-#define H3_CLK_MMC1_SAMPLE 75
-#define H3_CLK_MMC1_OUTPUT 76
-#define H3_CLK_MMC2 77
-#define H3_CLK_MMC2_SAMPLE 78
-#define H3_CLK_MMC2_OUTPUT 79
-#define H3_CLK_TS 80
-#define H3_CLK_CE 81
-#define H3_CLK_SPI0 82
-#define H3_CLK_SPI1 83
-#define H3_CLK_I2S0 84
-#define H3_CLK_I2S1 85
-#define H3_CLK_I2S2 86
-#define H3_CLK_SPDIF 87
-#define H3_CLK_USBPHY0 88
-#define H3_CLK_USBPHY1 89
-#define H3_CLK_USBPHY2 90
-#define H3_CLK_USBPHY3 91
-#define H3_CLK_USBOHCI0 92
-#define H3_CLK_USBOHCI1 93
-#define H3_CLK_USBOHCI2 94
-#define H3_CLK_USBOHCI3 95
-#define H3_CLK_DRAM 96
-#define H3_CLK_DRAM_VE 97
-#define H3_CLK_DRAM_CSI 98
-#define H3_CLK_DRAM_DEINTERLACE 99
-#define H3_CLK_DRAM_TS 100
-#define H3_CLK_DE 101
-#define H3_CLK_TCON0 102
-#define H3_CLK_TVE 103
-#define H3_CLK_DEINTERLACE 104
-#define H3_CLK_CSI_MISC 105
-#define H3_CLK_CSI_SCLK 106
-#define H3_CLK_CSI_MCLK 107
-#define H3_CLK_VE 108
-#define H3_CLK_AC_DIG 109
-#define H3_CLK_AVS 110
-#define H3_CLK_HDMI 111
-#define H3_CLK_HDMI_DDC 112
-#define H3_CLK_MBUS 113
-#define H3_CLK_GPU 114
-
void ccu_h3_register_clocks(struct aw_ccung_softc *sc);
#endif /* __CCU_H3_H__ */
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