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Sumit, 

It is my understanding that both interrupts are required in case (2) 
Service 
Interrupt Enabled. The first is to indicate to the host that it is time to 
read the
tag and set up the DMA engine. The second is the usual command 
ending interrupt.  Hard drive implementations do not support Service 
Interrupt  so I would defer to someone that has experience with Packet 
queuing. 

See figure 19 in ATA/ATAPI-6 state HI06:INTRQ_wait_B

Best Regards, 
DC

Dan Colegrove
Senior Technical Staff Member
Storage Technology Division
IBM Corporation

702-614-6119
702-614-7955 fax
Tie Line 280-9959 (IBM internal)
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Subject:        [temp t13] Service CMD question



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Does anybody know the correct answer to his inquiry?
I don't know if this is addressed specifically in the ATA-6 spec.
thanks in advance for your help

- Sumit


We have a question regarding a SERVICE interrupt described in
ATA6 as following:

***************************************************************
8.50.21 Enable/disable SERVICE interrupt
Subcommand codes 5Eh and DEh allow a host to enable or disable
the asserting of an interrupt pending when DRQ is set to one in
response to a SERVICE command.
***************************************************************

Question::
In the case of (2), is it required that the INTRQ signal be
asserted necessarily twice? Or is it possible to omit the second
 assertion (at the moment BSY gets low)?


We think that this description requires each signal be asserted
as following chart:

(1)When SERVICE interrupt is disabled

        SERVICE Cmd Issue
         |
         |   |----------------| Data Xfr
         V___                  ___
BSY    __|   |________________|   |______
              ________________
DRQ    ______|                |__________
                                   ___
INTRQ  ___________________________|   |__


(2)When SERVICE interrupt is enabled
          ___                  ___
BSY    __|   |________________|   |______
              ________________
DRQ    ______|                |__________
               ___                 ___
INTRQ  _______|   |_______________|   |__


Question::
In the case of (2), is it required that the INTRQ signal be
asserted necessarily twice? Or is it possible to omit the second
 assertion (at the moment BSY gets low)?



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