** This is the quasi-official and semi-temporary T13 email list server. **
On Sat, 8 Sep 2001 23:15:49 -0700, Ooi, Thien Ern wrote:
>I would like to clarify just exactly what conditions cause the device to
>assert an interrupt prior to a dma data transfer for a PACKET dma command.
>The device state in question is DPD3 "Ready_INTRQ" in the device PACKET-DMA
>command state diagram.
Please be very careful... There is an ERROR in the ATA/ATAPI-5 state
diagrams for PACKET DMA. This error should be fixed in the
ATA/ATAPI-5 "Errata" document and it should be fixed in the
ATA/ATAPI-6 state diagrams.
An ATAPI device executing a PACKET command in DMA mode should assert
interrupt only ONCE during the PACKET command executiong and that is
at the very end of the PACKET command execution.
>In T13/1321D revision 3, it shows that the device will enter the DPD3 state,
>and assert the interrupt when it is "ready to transfer data and nIEN=0".
>However, in T13/1410D revision 1c, this transition has been _removed_.
ATA/ATAPI-5 is wrong. ATA/ATAPI-6 is correct. You are not the only
ATAPI device designer that has been mislead by this error in the
state diagrams.
*** Hale Landis *** [EMAIL PROTECTED] ***
*** Niwot, CO USA *** www.ata-atapi.com ***
--
If you have any questions or wish to unsubscribe send a
message to Hale Landis, [EMAIL PROTECTED] To post to
this list server send your message to [EMAIL PROTECTED]
For questions concerning Thistle Grove Industries or TGI's
list services please send email to [EMAIL PROTECTED]
