> On Oct 27, 2017, at 9:38 AM, Mouse <mo...@rodents-montreal.org> wrote: > > ... > I would like to read the DMA buffer while DMA is still going on. That > is, I have a buffer of (say) 64K and the hardware is busily writing > into it; I want to read the buffer and see what the hardware has > written in the memory it has written and what used to be there in the > memory it hasn't. I'm fine if the CPU's view lags the hardware's view > slightly, but I do care about the CPU's view of the DMA write order > matching the hardware's: that is, if the CPU sees the value written by > a given DMA cycle, then the CPU must also see the values written by all > previous DMA cycles.
I'm not sure if that requirement is necessarily supported by hardware. For example, in machines that have incoherent DMA, I would think it isn't. paul