>>> [...access to DMA buffer while DMA in progress...ordering...] >> Hm! On such hardware, then, you can't count on any particular >> portion of a DMA transfer being visible until the whole transfer is >> finished? > Yes. I'm assuming here that the driver would do a data cache > invalidate (for the address range, if possible) at DMA end.
That sounds to me like something bus_dmamap_sync(BUS_DMASYNC_POSTREAD) would do. If so, it's not an issue for me; I'm perfectly fine with some such operation being part of any CPU access to the buffer during the transfer. > I don't know much about x86 style platforms. An example of the sort > of platform I mentioned would be the MIPS R5000. I still have some > scars from building a fast router on top of its incoherent DMA... Heh. Well, reading the x86 bus_dma implementation (amd64 doesn't seem to have a separate bus_dma implementation of its own) leads me to think it has no such issues; all POSTREAD does there is copy from the bounce buffer (if the transfer is bounced) and issue an lfence memory barrier. (Hmm, I wonder if the memory barrier needs to be before the memcpy....) /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML [email protected] / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
