Le sam. 15 déc. 2018 à 15:27, Jason Thorpe <thor...@me.com> a écrit : > We can buy ourselves some time on aarch64 by using a different page size, > yes? iOS, for example, uses 16KiB VM pages (backed by 4KiB or 16KiB physical > pages, depending on the specific CPU type). I don't think the ARM eabi has > the same section alignment issue that made the 4K/8K page size thing on m68k > such a pain. >
Bigger physical pages also reduce size of page tables (big deal if it e.g. allows to reduce e.g. 4-level to 3-level mapping, but even "just" factor or two or four is very good) and hence speed up page faults, and improve TLB utilization. It's really good thing overall and something which is very desirable on monster memory machines. Jaromir
