Joachim Strömbergson wrote: > Registers for key and data has also been changed syntax wise to use > Verilog two dimensional arrays. All tools (simulators, synthesis/build > tools) I have access to including ISE, ModelSim, Quartus parses this > correctly.
Please also see if yosys ( https://github.com/clifford/yosys ) does? //Peter _______________________________________________ Tech mailing list Tech@cryptech.is https://lists.cryptech.is/listinfo/tech
