Aloha! Peter Stuge wrote: > Joachim Strömbergson wrote: >> Registers for key and data has also been changed syntax wise to use >> Verilog two dimensional arrays. All tools (simulators, synthesis/build >> tools) I have access to including ISE, ModelSim, Quartus parses this >> correctly. > > Please also see if yosys ( https://github.com/clifford/yosys ) does?
After patching the core-code to use fix the isse with process local two dimensional arrays synthesis and tech mapping in Yosys completes (after four hour processing time). See included result report for cell usage. -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. ======================================================================== Joachim Strömbergson Secworks AB joac...@secworks.se ========================================================================
=== chacha ===
Number of wires: 3009
Number of wire bits: 6069
Number of public wires: 44
Number of public wire bits: 2294
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 4648
$_AND_ 990
$_AOI3_ 278
$_AOI4_ 8
$_DFF_P_ 840
$_MUX_ 1354
$_NAND_ 25
$_NOR_ 17
$_NOT_ 567
$_OAI3_ 21
$_OAI4_ 13
$_OR_ 534
chacha_core 1
=== chacha_core ===
Number of wires: 9073
Number of wire bits: 14842
Number of public wires: 101
Number of public wire bits: 4794
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 11664
$_AND_ 2878
$_AOI3_ 277
$_AOI4_ 6
$_DFF_P_ 1100
$_MUX_ 1628
$_NAND_ 1481
$_NOR_ 270
$_NOT_ 1060
$_OAI3_ 544
$_OAI4_ 146
$_OR_ 786
$_XNOR_ 229
$_XOR_ 1255
chacha_qr 4
=== chacha_qr ===
Number of wires: 1048
Number of wire bits: 1606
Number of public wires: 18
Number of public wire bits: 576
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1158
$_AND_ 135
$_AOI3_ 92
$_NAND_ 47
$_NOR_ 100
$_NOT_ 239
$_OAI3_ 66
$_OR_ 78
$_XNOR_ 96
$_XOR_ 305
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