I have not got back to the ST Link, but I've been trying to use Impact
to independently verify the use of the cryptech_upload script to reflash
the bitstream PROM.
Using cryptech_upload i get a checksum of CRC-32 0x6f23447b.
Using the alpha_fmc.bit from the same tarball cryptech_upload is
extracting and generating a .mcs file as outlined in
https://www.xilinx.com/support/documentation/application.../xapp586-spi-flash.pdf
I get "All Checksum calculations are performed on the address range
spanned by the configuration file.
'1': Calculated checksum matches expected checksum, 006303f92" when
programming with this generated .mcs
The FPGA ready led comes on green but gives core error message when
trying to set masterkey.
Re-flashed using the cryptech_upload --fpga --user wheel command. Once
again this command resulted in a checksum of 0x6f23447b and core
operations were back to normal. I then performed a "Get Device Checksum"
in impact and got this
"All Checksum calculations are performed on the address range spanned by
the configuration file.
ERROR:Cse - '1': The calculated checksum (0x063005bd) differs from the
expected checksum (0x06303f92).
PROGRESS_END - End Operation."
On 05/04/2018 12:00 AM, Rob Austein wrote:
On Fri, 04 May 2018 00:00:10 -0400, Michael wrote:
One curious thing, if I use the "firmware upload" command while in
cryptech_console, I see the blue LED flash as described in the
documentation indicating the bootloader is being accessed. Calling
cryptech_upload from the terminal does not seem to reset to the
bootloader (no flashing blue LED)
From your description, cryptech_upload isn't getting that far in the
dialog. Add the --debug option if you want to see the details.
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