13.05.2018 17:32, Rob Austein пишет: > On Sun, 13 May 2018 05:55:13 -0400, Peter Stuge wrote: > ... >> Tamper detection can fail in two ways: >> 1. Detection wipes keys too often. >> 2. Detection doesn't wipe key when attacked. >> I think which failure mode one prefers depends on the application, > > So maybe we want physical hardware fast enough to support either mode, > with the choice of mode selectable when synthesizing the Verilog.
Yes, if we use a tiny FPGA as the master key storage, then it's up to the firmware of that FPGA whether to directly connect tamper inputs to resets or to synchronize them beforehand. This can be changed on the fly without board redesign. Good point.
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