Fredrik Thulin wrote: > > > 2. Add CTS+RTS to the UART interface > > > > I discovered that CTS+RTS are actually already connected to the USER FTDI > > in the rev03 schematic, but not to the MGMT FTDI. So at least some of the > > routing already exists! > > I must be misunderstanding what you mean with "connected" because I see both > FT_MGMT_CTS and FT_MGMT_RTS in the schematic and on the KiCAD converted board > layout. See the attached screenshot with FT_MGMT_CTS highlighted.
You're absolutely right, the signals are routed for both ports. Great! I don't know why I thought that it wasn't in the schematic. It's right there. Thanks for the correction. If we want to include a header for a USB daughterboard also in a new design (I think it is still useful) then let's please use a 2x5 header with this pinout, which should be uncontroversial since it's backwards compatible and just adds signals that I forgot to ask for in rev03. GND 1 2 VBUS D+ 3 4 D- TXD 5 6 RXD RTS 7 8 CTS RST 9 10 VCCO_3V3 Pins 1-6 remain unchanged from rev03 J2,J3. Signal names for pins 5&6 changed, and all signal names are as seen from the STM32, ie. pin 5 transmits data from STM32 to a daughterboard. I think this makes more sense than the current net names which are as seen from the USB chip. Pin 9 is an active low reset for the onboard interface. Only when pin 9 is connected to GND on the daughterboard is it permitted to drive D+, D-, RXD and CTS. Full disclosure: We assume this header on our first PCI Express test board, so this particular pinout could make our lives a little easier. //Peter _______________________________________________ Tech mailing list Tech@cryptech.is https://lists.cryptech.is/listinfo/tech
