hi,
following diff brings support for ICH10 R BM LF chip as well, basic tests
done by matthew at dempsky org (thanks).
no changes to the code except for binging in new defines
(this is again a patch for my previous patch for i82574L
.
diff -uNp ./i82574/if_em.c ./iCH10/if_em.c
--- ./i82574/if_em.c Thu Jun 18 14:53:03 2009
+++ ./iCH10/if_em.c Fri Jun 19 22:34:00 2009
@@ -138,7 +138,9 @@ const struct pci_matchid em_devices[] = {
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M },
- { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }
};
/*********************************************************************
diff -uNp ./i82574/if_em_hw.c ./iCH10/if_em_hw.c
--- ./i82574/if_em_hw.c Thu Jun 18 14:53:03 2009
+++ ./iCH10/if_em_hw.c Fri Jun 19 22:33:44 2009
@@ -481,6 +481,8 @@ em_set_mac_type(struct em_hw *hw)
case E1000_DEV_ID_ICH9_IGP_C:
case E1000_DEV_ID_ICH9_IGP_M:
case E1000_DEV_ID_ICH9_IGP_M_AMT:
+ case E1000_DEV_ID_ICH10_R_BM_LM:
+ case E1000_DEV_ID_ICH10_R_BM_LF:
hw->mac_type = em_ich9lan;
break;
default:
@@ -3622,7 +3624,6 @@ em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr
{
uint32_t i;
uint32_t mdic = 0;
- const uint32_t phy_addr = 1;
DEBUGFUNC("em_read_phy_reg_ex");
@@ -3637,7 +3638,7 @@ em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr
* PHY to retrieve the desired data.
*/
mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
- (phy_addr << E1000_MDIC_PHY_SHIFT) |
+ (hw->phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_READ));
E1000_WRITE_REG(hw, MDIC, mdic);
@@ -3675,7 +3676,7 @@ em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
- mdic = ((reg_addr) | (phy_addr << 5) |
+ mdic = ((reg_addr) | (hw->phy_addr << 5) |
(PHY_OP_READ << 10) | (PHY_SOF << 12));
em_shift_out_mdi_bits(hw, mdic, 14);
@@ -3766,7 +3767,6 @@ em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_add
{
uint32_t i;
uint32_t mdic = 0;
- const uint32_t phy_addr = 1;
DEBUGFUNC("em_write_phy_reg_ex");
@@ -3782,7 +3782,7 @@ em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_add
*/
mdic = (((uint32_t) phy_data) |
(reg_addr << E1000_MDIC_REG_SHIFT) |
- (phy_addr << E1000_MDIC_PHY_SHIFT) |
+ (hw->phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_WRITE));
E1000_WRITE_REG(hw, MDIC, mdic);
@@ -3811,7 +3811,7 @@ em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_add
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
- mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
+ mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (hw->phy_addr << 7) |
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
mdic <<= 16;
mdic |= (uint32_t) phy_data;
@@ -4102,6 +4102,9 @@ em_detect_gig_phy(struct em_hw *hw)
if (hw->phy_id != 0)
return E1000_SUCCESS;
+ /* default phy address, most phys reside here, but not all (ICH10) */
+ hw->phy_addr = 1;
+
/* The 82571 firmware may still be configuring the PHY. In this
* case, we cannot access the PHY until the configuration is done. So
* we explicitly set the PHY values. */
@@ -4132,66 +4135,69 @@ em_detect_gig_phy(struct em_hw *hw)
hw->phy_type = em_phy_gg82563;
/* Read the PHY ID Registers to identify which PHY is onboard. */
- ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
- if (ret_val)
- return ret_val;
+ for(hw->phy_addr=1; (!match)&&(hw->phy_addr<4); hw->phy_addr++) {
+ ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+ if (ret_val)
+ return ret_val;
- hw->phy_id = (uint32_t) (phy_id_high << 16);
- usec_delay(20);
- ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
- if (ret_val)
- return ret_val;
+ hw->phy_id = (uint32_t) (phy_id_high << 16);
+ usec_delay(20);
+ ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+ if (ret_val)
+ return ret_val;
- hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
- hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
+ hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
+ hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
- switch (hw->mac_type) {
- case em_82543:
- if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
- break;
- case em_82544:
- if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
- break;
- case em_82540:
- case em_82545:
- case em_82545_rev_3:
- case em_82546:
- case em_82546_rev_3:
- if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
- break;
- case em_82541:
- case em_82541_rev_2:
- case em_82547:
- case em_82547_rev_2:
- if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
- break;
- case em_82573:
- if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
- break;
- case em_82574:
- if (hw->phy_id == BME1000_E_PHY_ID) match = TRUE;
- break;
- case em_80003es2lan:
- if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
- break;
- case em_ich8lan:
- case em_ich9lan:
- if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
- if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
- if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
- if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
- break;
- default:
- DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
- return -E1000_ERR_CONFIG;
- }
- phy_init_status = em_set_phy_type(hw);
+ switch (hw->mac_type) {
+ case em_82543:
+ if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
+ break;
+ case em_82544:
+ if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
+ break;
+ case em_82540:
+ case em_82545:
+ case em_82545_rev_3:
+ case em_82546:
+ case em_82546_rev_3:
+ if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
+ break;
+ case em_82541:
+ case em_82541_rev_2:
+ case em_82547:
+ case em_82547_rev_2:
+ if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
+ break;
+ case em_82573:
+ if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
+ break;
+ case em_82574:
+ if (hw->phy_id == BME1000_E_PHY_ID) match = TRUE;
+ break;
+ case em_80003es2lan:
+ if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
+ break;
+ case em_ich8lan:
+ case em_ich9lan:
+ if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == BME1000_E_PHY_ID) match = TRUE;
+ break;
+ default:
+ DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
+ return -E1000_ERR_CONFIG;
+ }
+ phy_init_status = em_set_phy_type(hw);
- if ((match) && (phy_init_status == E1000_SUCCESS)) {
- DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
- return E1000_SUCCESS;
+ if ((match) && (phy_init_status == E1000_SUCCESS)) {
+ DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
+ return E1000_SUCCESS;
+ }
+ DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
}
- DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
return -E1000_ERR_PHY;
}
