> > Date: Thu, 15 Oct 2015 17:23:21 +0000
> > From: Miod Vallat <m...@online.fr>
> >
> > The following diff attempts to fix two small bge(4) bugs:
> >
> > - the first chunk fixes what seems to be a logic error on BCM 5720,
> > where the code attemps to preserve the state of four bits, but these
> > have actually already been set in the local variable by the call to
> > bge_dma_swap_options() immediately above. For some reason the
> > bge_dma_swap_options() logic does not affect BCM 5762, and I'm not
> > sure whether this is a bug or not.
> >
> > - the second chunk repairs BCM5704 A3 support, as found on some G5 Xserve
> > (RackMac3,1), by using the proper function pointer to write a magic
> > register. Apparently, using the wrong function only works once, which
> > allows the driver to attach, but as soon as you attempt to give it an
> > IP address, the machine freezes without that change.
>
> This chunk doesn't make sense to me. The code is supposed to write a
> magic value into SRAM, not into a register.
>
> I suspect that the real issue is that we disable the MAC memory
> arbiter in bge_stop(). The MAC memory arbiter has to be enabled for
> bge_writemem_ind() to work, but bge_reset() only enables it later
> after it resets the chip. Does the diff below help?
No; with this diff the system freezes at attach time.
> Index: if_bge.c
> ===================================================================
> RCS file: /home/cvs/src/sys/dev/pci/if_bge.c,v
> retrieving revision 1.369
> diff -u -p -r1.369 if_bge.c
> --- if_bge.c 19 Jul 2015 06:28:12 -0000 1.369
> +++ if_bge.c 16 Oct 2015 19:48:45 -0000
> @@ -3216,6 +3216,13 @@ bge_reset(struct bge_softc *sc)
> cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
> command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
>
> + /* Enable memory arbiter. */
> + if (BGE_IS_5714_FAMILY(sc)) {
> + val = CSR_READ_4(sc, BGE_MARB_MODE);
> + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
> + } else
> + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
> +
> pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
> BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
> BGE_PCIMISCCTL_ENDIAN_WORDSWAP | BGE_PCIMISCCTL_PCISTATE_RW);
