Hi,
next up on the list is the StrongARM and IXP12x0.
This diff removes most, but keeps the SA1100 headers,
which are still used by zaurus.
Patrick
diff --git sys/arch/arm/arm/bus_space_asm_generic.S
sys/arch/arm/arm/bus_space_asm_generic.S
index b96ca4a..5e610e2 100644
--- sys/arch/arm/arm/bus_space_asm_generic.S
+++ sys/arch/arm/arm/bus_space_asm_generic.S
@@ -50,7 +50,7 @@ ENTRY(generic_bs_r_1)
ldrb r0, [r1, r2]
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_r_2)
ldrh r0, [r1, r2]
mov pc, lr
@@ -68,7 +68,7 @@ ENTRY(generic_bs_w_1)
strb r3, [r1, r2]
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_w_2)
strh r3, [r1, r2]
mov pc, lr
@@ -96,7 +96,7 @@ ENTRY(generic_bs_rm_1)
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_rm_2)
add r0, r1, r2
mov r1, r3
@@ -144,7 +144,7 @@ ENTRY(generic_bs_wm_1)
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_wm_2)
add r0, r1, r2
mov r1, r3
@@ -192,7 +192,7 @@ ENTRY(generic_bs_rr_1)
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_rr_2)
add r0, r1, r2
mov r1, r3
@@ -240,7 +240,7 @@ ENTRY(generic_bs_wr_1)
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_wr_2)
add r0, r1, r2
mov r1, r3
@@ -287,7 +287,7 @@ ENTRY(generic_bs_sr_1)
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_sr_2)
add r0, r1, r2
mov r1, r3
@@ -319,7 +319,7 @@ ENTRY(generic_bs_sr_4)
* copy region
*/
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(generic_armv4_bs_c_2)
add r0, r1, r2
ldr r2, [sp, #0]
diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
index c5cae81..593bdac 100644
--- sys/arch/arm/arm/cpu.c
+++ sys/arch/arm/arm/cpu.c
@@ -87,7 +87,6 @@ enum cpu_class {
CPU_CLASS_ARM9ES,
CPU_CLASS_ARM9EJS,
CPU_CLASS_ARM10E,
- CPU_CLASS_SA1,
CPU_CLASS_XSCALE,
CPU_CLASS_ARM11J,
CPU_CLASS_ARMv7
@@ -100,36 +99,6 @@ static const char * const generic_steppings[16] = {
"rev 12", "rev 13", "rev 14", "rev 15"
};
-static const char * const sa110_steppings[16] = {
- "rev 0", "step J", "step K", "step S",
- "step T", "rev 5", "rev 6", "rev 7",
- "rev 8", "rev 9", "rev 10", "rev 11",
- "rev 12", "rev 13", "rev 14", "rev 15"
-};
-
-static const char * const sa1100_steppings[16] = {
- "rev 0", "step B", "step C", "rev 3",
- "rev 4", "rev 5", "rev 6", "rev 7",
- "step D", "step E", "rev 10" "step G",
- "rev 12", "rev 13", "rev 14", "rev 15"
-};
-
-static const char * const sa1110_steppings[16] = {
- "step A-0", "rev 1", "rev 2", "rev 3",
- "step B-0", "step B-1", "step B-2", "step B-3",
- "step B-4", "step B-5", "rev 10", "rev 11",
- "rev 12", "rev 13", "rev 14", "rev 15"
-};
-
-static const char * const ixp12x0_steppings[16] = {
- "(IXP1200 step A)", "(IXP1200 step B)",
- "rev 2", "(IXP1200 step C)",
- "(IXP1200 step D)", "(IXP1240/1250 step A)",
- "(IXP1240 step B)", "(IXP1250 step B)",
- "rev 8", "rev 9", "rev 10", "rev 11",
- "rev 12", "rev 13", "rev 14", "rev 15"
-};
-
static const char * const xscale_steppings[16] = {
"step A-0", "step A-1", "step B-0", "step C-0",
"step D-0", "rev 5", "rev 6", "rev 7",
@@ -206,16 +175,6 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
generic_steppings },
- { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
- sa110_steppings },
- { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
- sa1100_steppings },
- { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110",
- sa1110_steppings },
-
- { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200",
- ixp12x0_steppings },
-
{ CPU_ID_80200, CPU_CLASS_XSCALE, "i80200",
xscale_steppings },
@@ -323,7 +282,6 @@ const struct cpu_classtab cpu_classes[] = {
{ "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
{ "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
{ "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
- { "SA-1", "CPU_SA1100" }, /* CPU_CLASS_SA1 */
{ "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
{ "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
{ "ARMv7", "CPU_ARMv7" } /* CPU_CLASS_ARMv7 */
@@ -392,7 +350,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
case CPU_CLASS_ARM9ES:
case CPU_CLASS_ARM9EJS:
case CPU_CLASS_ARM10E:
- case CPU_CLASS_SA1:
case CPU_CLASS_XSCALE:
case CPU_CLASS_ARM11J:
case CPU_CLASS_ARMv7:
@@ -457,9 +414,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
case CPU_CLASS_ARMv7:
#endif
-#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
- case CPU_CLASS_SA1:
-#endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
case CPU_CLASS_XSCALE:
diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
index 5409ffc..a0472f6 100644
--- sys/arch/arm/arm/cpufunc.c
+++ sys/arch/arm/arm/cpufunc.c
@@ -327,121 +327,6 @@ struct cpu_functions armv7_cpufuncs = {
};
#endif /* CPU_ARMv7 */
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-struct cpu_functions sa11x0_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- sa1_setttb, /* setttb */
- cpufunc_dfsr, /* dfsr */
- cpufunc_dfar, /* dfar */
- cpufunc_ifsr, /* ifsr */
- cpufunc_ifar, /* ifar */
-
- /* TLB functions */
-
- armv4_tlb_flushID, /* tlb_flushID */
- sa1_tlb_flushID_SE, /* tlb_flushID_SE */
- armv4_tlb_flushI, /* tlb_flushI */
- (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
- armv4_tlb_flushD, /* tlb_flushD */
- armv4_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- sa1_cache_syncI, /* icache_sync_all */
- sa1_cache_syncI_rng, /* icache_sync_range */
-
- sa1_cache_purgeD, /* dcache_wbinv_all */
- sa1_cache_purgeD_rng, /* dcache_wbinv_range */
-/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
- sa1_cache_cleanD_rng, /* dcache_wb_range */
-
- sa1_cache_purgeID, /* idcache_wbinv_all */
- sa1_cache_purgeID_rng, /* idcache_wbinv_range */
-
- cpufunc_nullop, /* sdcache_wbinv_all */
- (void *)cpufunc_nullop, /* sdcache_wbinv_range */
- (void *)cpufunc_nullop, /* sdcache_inv_range */
- (void *)cpufunc_nullop, /* sdcache_wb_range */
-
- /* Other functions */
-
- sa11x0_drain_readbuf, /* flush_prefetchbuf */
- armv4_drain_writebuf, /* drain_writebuf */
-
- sa11x0_cpu_sleep, /* sleep */
-
- /* Soft functions */
- sa11x0_context_switch, /* context_switch */
- sa11x0_setup /* cpu setup */
-};
-#endif /* CPU_SA1100 || CPU_SA1110 */
-
-#ifdef CPU_IXP12X0
-struct cpu_functions ixp12x0_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- sa1_setttb, /* setttb */
- cpufunc_dfsr, /* dfsr */
- cpufunc_dfar, /* dfar */
- cpufunc_ifsr, /* ifsr */
- cpufunc_ifar, /* ifar */
-
- /* TLB functions */
-
- armv4_tlb_flushID, /* tlb_flushID */
- sa1_tlb_flushID_SE, /* tlb_flushID_SE */
- armv4_tlb_flushI, /* tlb_flushI */
- (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
- armv4_tlb_flushD, /* tlb_flushD */
- armv4_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- sa1_cache_syncI, /* icache_sync_all */
- sa1_cache_syncI_rng, /* icache_sync_range */
-
- sa1_cache_purgeD, /* dcache_wbinv_all */
- sa1_cache_purgeD_rng, /* dcache_wbinv_range */
-/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
- sa1_cache_cleanD_rng, /* dcache_wb_range */
-
- sa1_cache_purgeID, /* idcache_wbinv_all */
- sa1_cache_purgeID_rng, /* idcache_wbinv_range */
-
- cpufunc_nullop, /* sdcache_wbinv_all */
- (void *)cpufunc_nullop, /* sdcache_wbinv_range */
- (void *)cpufunc_nullop, /* sdcache_inv_range */
- (void *)cpufunc_nullop, /* sdcache_wb_range */
-
- /* Other functions */
-
- ixp12x0_drain_readbuf, /* flush_prefetchbuf */
- armv4_drain_writebuf, /* drain_writebuf */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
- ixp12x0_context_switch, /* context_switch */
- ixp12x0_setup /* cpu setup */
-};
-#endif /* CPU_IXP12X0 */
-
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
struct cpu_functions xscale_cpufuncs = {
@@ -590,58 +475,6 @@ get_cachetype_cp15()
}
#endif /* ARM7TDMI || ARM9 || XSCALE */
-#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
-/* Cache information for CPUs without cache type registers. */
-struct cachetab {
- u_int32_t ct_cpuid;
- int ct_pcache_type;
- int ct_pcache_unified;
- int ct_pdcache_size;
- int ct_pdcache_line_size;
- int ct_pdcache_ways;
- int ct_picache_size;
- int ct_picache_line_size;
- int ct_picache_ways;
-};
-
-struct cachetab cachetab[] = {
- /* cpuid, cache type, u, dsiz, ls, wy, isiz, ls, wy */
- /* XXX is this type right for SA-1? */
- { CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
- { CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
- { CPU_ID_IXP1200, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, /*
XXX */
- { 0, 0, 0, 0, 0, 0, 0, 0}
-};
-
-static void get_cachetype_table (void);
-
-static void
-get_cachetype_table()
-{
- int i;
- u_int32_t cpuid = cpufunc_id();
-
- for (i = 0; cachetab[i].ct_cpuid != 0; i++) {
- if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) {
- arm_pcache_type = cachetab[i].ct_pcache_type;
- arm_pcache_unified = cachetab[i].ct_pcache_unified;
- arm_pdcache_size = cachetab[i].ct_pdcache_size;
- arm_pdcache_line_size =
- cachetab[i].ct_pdcache_line_size;
- arm_pdcache_ways = cachetab[i].ct_pdcache_ways;
- arm_picache_size = cachetab[i].ct_picache_size;
- arm_picache_line_size =
- cachetab[i].ct_picache_line_size;
- arm_picache_ways = cachetab[i].ct_picache_ways;
- }
- }
- arm_dcache_align = arm_pdcache_line_size;
-
- arm_dcache_align_mask = arm_dcache_align - 1;
-}
-
-#endif /* SA110 || SA1100 || SA1111 || IXP12X0 */
-
#ifdef CPU_ARMv7
void arm_get_cachetype_cp15v7 (void);
int arm_dcache_l2_nsets;
@@ -880,41 +713,6 @@ set_cpufuncs()
return 0;
}
#endif /* CPU_ARMv7 */
-#ifdef CPU_SA1100
- if (cputype == CPU_ID_SA1100) {
- cpufuncs = sa11x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
- get_cachetype_table();
- pmap_pte_init_sa1();
-
- /* Use powersave on this CPU. */
- cpu_do_powersave = 1;
-
- return 0;
- }
-#endif /* CPU_SA1100 */
-#ifdef CPU_SA1110
- if (cputype == CPU_ID_SA1110) {
- cpufuncs = sa11x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
- get_cachetype_table();
- pmap_pte_init_sa1();
-
- /* Use powersave on this CPU. */
- cpu_do_powersave = 1;
-
- return 0;
- }
-#endif /* CPU_SA1110 */
-#ifdef CPU_IXP12X0
- if (cputype == CPU_ID_IXP1200) {
- cpufuncs = ixp12x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1;
- get_cachetype_table();
- pmap_pte_init_sa1();
- return 0;
- }
-#endif /* CPU_IXP12X0 */
#ifdef CPU_XSCALE_80200
if (cputype == CPU_ID_80200) {
int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
@@ -1168,65 +966,6 @@ armv7_setup()
}
#endif /* CPU_ARMv7 */
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-void
-sa11x0_setup()
-{
- int cpuctrl, cpuctrlmask;
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
- | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
- | CPU_CONTROL_AFLT_ENABLE;
- cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
- | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
- | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
- | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
- | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
-
- if (vector_page == ARM_VECTORS_HIGH)
- cpuctrl |= CPU_CONTROL_VECRELOC;
-
- /* Clear out the cache */
- cpu_idcache_wbinv_all();
-
- /* Set the control register */
- cpu_control(0xffffffff, cpuctrl);
-}
-#endif /* CPU_SA1100 || CPU_SA1110 */
-
-#if defined(CPU_IXP12X0)
-void
-ixp12x0_setup()
-{
- int cpuctrl, cpuctrlmask;
-
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE
- | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_AFLT_ENABLE;
- cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE
- | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE
- | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE
- | CPU_CONTROL_VECRELOC;
-
- if (vector_page == ARM_VECTORS_HIGH)
- cpuctrl |= CPU_CONTROL_VECRELOC;
-
- /* Clear out the cache */
- cpu_idcache_wbinv_all();
-
- /* Set the control register */
- curcpu()->ci_ctrl = cpuctrl;
- /* cpu_control(0xffffffff, cpuctrl); */
- cpu_control(cpuctrlmask, cpuctrl);
-}
-#endif /* CPU_IXP12X0 */
-
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
void
diff --git sys/arch/arm/arm/cpufunc_asm_sa1.S sys/arch/arm/arm/cpufunc_asm_sa1.S
deleted file mode 100644
index 079cc9d..0000000
--- sys/arch/arm/arm/cpufunc_asm_sa1.S
+++ /dev/null
@@ -1,291 +0,0 @@
-/* $OpenBSD: cpufunc_asm_sa1.S,v 1.6 2016/01/31 00:14:50 jsg Exp $ */
-/* $NetBSD: cpufunc_asm_sa1.S,v 1.8 2002/08/17 16:36:32 thorpej Exp $
*/
-
-/*
- * Copyright (c) 1997,1998 Mark Brinicombe.
- * Copyright (c) 1997 Causality Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Causality Limited.
- * 4. The name of Causality Limited may not be used to endorse or promote
- * products derived from this software without specific prior written
- * permission.
- *
- * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * SA-1 assembly functions for CPU / MMU / TLB specific operations
- */
-
-#include <machine/cpu.h>
-#include <machine/asm.h>
-
-/*
- * Functions to set the MMU Translation Table Base register
- *
- * We need to clean and flush the cache as it uses virtual
- * addresses that are about to change.
- */
-ENTRY(sa1_setttb)
- mrs r3, cpsr
- orr r1, r3, #(PSR_I | PSR_F)
- msr cpsr_c, r1
-
- stmfd sp!, {r0-r3, lr}
- bl _C_LABEL(sa1_cache_cleanID)
- ldmfd sp!, {r0-r3, lr}
- mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
- mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
-
- /* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0
-
- /* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
-
- /* The cleanID above means we only need to flush the I cache here */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
-
- /* Make sure that pipeline is emptied */
- mov r0, r0
- mov r0, r0
-
- msr cpsr_c, r3
- mov pc, lr
-
-/*
- * TLB functions
- */
-ENTRY(sa1_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
- mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
- mov pc, lr
-
-/*
- * Cache functions
- */
-ENTRY(sa1_cache_flushID)
- mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
- mov pc, lr
-
-ENTRY(sa1_cache_flushI)
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
- mov pc, lr
-
-ENTRY(sa1_cache_flushD)
- mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
- mov pc, lr
-
-ENTRY(sa1_cache_flushD_SE)
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
- mov pc, lr
-
-ENTRY(sa1_cache_cleanD_E)
- mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- mov pc, lr
-
-/*
- * Information for the SA-1 cache clean/purge functions:
- *
- * * Virtual address of the memory region to use
- * * Size of memory region
- */
- .data
-
- .global _C_LABEL(sa1_cache_clean_addr)
-_C_LABEL(sa1_cache_clean_addr):
- .word 0xf0000000
-
- .global _C_LABEL(sa1_cache_clean_size)
-_C_LABEL(sa1_cache_clean_size):
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
- .word 0x00004000
-#else
- .word 0x00008000
-#endif
-
- .text
-
-.Lsa1_cache_clean_addr:
- .word _C_LABEL(sa1_cache_clean_addr)
-.Lsa1_cache_clean_size:
- .word _C_LABEL(sa1_cache_clean_size)
-
-#define SA1_CACHE_CLEAN_BLOCK
\
- mrs r3, cpsr ; \
- orr r0, r3, #(PSR_I | PSR_F) ; \
- msr cpsr_c, r0
-
-#define SA1_CACHE_CLEAN_UNBLOCK
\
- msr cpsr_c, r3
-
-#ifdef DOUBLE_CACHE_CLEAN_BANK
-#define SA1_DOUBLE_CACHE_CLEAN_BANK
\
- eor r0, r0, r1 ; \
- str r0, [r2]
-#else
-#define SA1_DOUBLE_CACHE_CLEAN_BANK /* nothing */
-#endif /* DOUBLE_CACHE_CLEAN_BANK */
-
-#define SA1_CACHE_CLEAN_PROLOGUE
\
- SA1_CACHE_CLEAN_BLOCK ; \
- ldr r2, .Lsa1_cache_clean_addr ; \
- ldmia r2, {r0, r1} ; \
- SA1_DOUBLE_CACHE_CLEAN_BANK
-
-#define SA1_CACHE_CLEAN_EPILOGUE
\
- SA1_CACHE_CLEAN_UNBLOCK
-
-ENTRY_NP(sa1_cache_syncI)
-ENTRY_NP(sa1_cache_purgeID)
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
-ENTRY_NP(sa1_cache_cleanID)
-ENTRY_NP(sa1_cache_purgeD)
-ENTRY(sa1_cache_cleanD)
- SA1_CACHE_CLEAN_PROLOGUE
-
-1: ldr r2, [r0], #32
- subs r1, r1, #32
- bne 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
-
- SA1_CACHE_CLEAN_EPILOGUE
- mov pc, lr
-
-ENTRY(sa1_cache_purgeID_E)
- mcr p15, 0, r0, c7, c10, 1 /* clean dcache entry */
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
- mov pc, lr
-
-ENTRY(sa1_cache_purgeD_E)
- mcr p15, 0, r0, c7, c10, 1 /* clean dcache entry */
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
- mov pc, lr
-
-/*
- * Soft functions
- */
-/* sa1_cache_syncI is identical to sa1_cache_purgeID */
-
-ENTRY(sa1_cache_cleanID_rng)
-ENTRY(sa1_cache_cleanD_rng)
- cmp r1, #0x4000
- bcs _C_LABEL(sa1_cache_cleanID)
-
- and r2, r0, #0x1f
- add r1, r1, r2
- bic r0, r0, #0x1f
-
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- add r0, r0, #32
- subs r1, r1, #32
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mov pc, lr
-
-ENTRY(sa1_cache_purgeID_rng)
- cmp r1, #0x4000
- bcs _C_LABEL(sa1_cache_purgeID)
-
- and r2, r0, #0x1f
- add r1, r1, r2
- bic r0, r0, #0x1f
-
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
- add r0, r0, #32
- subs r1, r1, #32
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
- mov pc, lr
-
-ENTRY(sa1_cache_purgeD_rng)
- cmp r1, #0x4000
- bcs _C_LABEL(sa1_cache_purgeD)
-
- and r2, r0, #0x1f
- add r1, r1, r2
- bic r0, r0, #0x1f
-
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
- add r0, r0, #32
- subs r1, r1, #32
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mov pc, lr
-
-ENTRY(sa1_cache_syncI_rng)
- cmp r1, #0x4000
- bcs _C_LABEL(sa1_cache_syncI)
-
- and r2, r0, #0x1f
- add r1, r1, r2
- bic r0, r0, #0x1f
-
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- add r0, r0, #32
- subs r1, r1, #32
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
-
- mov pc, lr
-
-/*
- * Context switch.
- *
- * These is the CPU-specific parts of the context switcher cpu_switch()
- * These functions actually perform the TTB reload.
- *
- * NOTE: Special calling convention
- * r1, r4-r13 must be preserved
- */
-#if defined(CPU_SA110)
-ENTRY(sa110_context_switch)
- /*
- * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
- * Thus the data cache will contain only kernel data and the
- * instruction cache will contain only kernel code, and all
- * kernel mappings are shared by all processes.
- */
-
- /* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0
-
- /* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
-
- /* Make sure that pipeline is emptied */
- mov r0, r0
- mov r0, r0
- mov pc, lr
-#endif
diff --git sys/arch/arm/arm/pmap.c sys/arch/arm/arm/pmap.c
index 62d098d..b6d453e 100644
--- sys/arch/arm/arm/pmap.c
+++ sys/arch/arm/arm/pmap.c
@@ -3045,7 +3045,7 @@ pmap_reference(pmap_t pm)
* StrongARM accesses to non-cached pages are non-burst making writing
* _any_ bulk data very slow.
*/
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
+#if ARM_MMU_GENERIC == 1
void
pmap_zero_page_generic(struct vm_page *pg)
{
@@ -3069,7 +3069,7 @@ pmap_zero_page_generic(struct vm_page *pg)
bzero_page(cdstp);
cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
}
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
+#endif /* ARM_MMU_GENERIC == 1 */
#if ARM_MMU_XSCALE == 1
void
@@ -3105,7 +3105,7 @@ pmap_zero_page_xscale(struct vm_page *pg)
* hook points. The same comment regarding cachability as in
* pmap_zero_page also applies here.
*/
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
+#if ARM_MMU_GENERIC == 1
void
pmap_copy_page_generic(struct vm_page *src_pg, struct vm_page *dst_pg)
{
@@ -3144,7 +3144,7 @@ pmap_copy_page_generic(struct vm_page *src_pg, struct
vm_page *dst_pg)
cpu_dcache_inv_range(csrcp, PAGE_SIZE);
cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
}
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
+#endif /* ARM_MMU_GENERIC == 1 */
#if ARM_MMU_XSCALE == 1
void
@@ -4380,7 +4380,7 @@ pt_entry_t pte_l2_s_proto;
void (*pmap_copy_page_func)(struct vm_page *, struct vm_page *);
void (*pmap_zero_page_func)(struct vm_page *);
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
+#if ARM_MMU_GENERIC == 1
void
pmap_pte_init_generic(void)
{
@@ -4438,7 +4438,7 @@ pmap_pte_init_generic(void)
pmap_copy_page_func = pmap_copy_page_generic;
pmap_zero_page_func = pmap_zero_page_generic;
}
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
+#endif /* ARM_MMU_GENERIC == 1 */
#if defined(CPU_ARM10)
void
@@ -4546,27 +4546,6 @@ pmap_pte_init_armv7(void)
}
#endif /* CPU_ARMv7 */
-#if ARM_MMU_SA1 == 1
-void
-pmap_pte_init_sa1(void)
-{
-
- /*
- * The StrongARM SA-1 cache does not have a write-through
- * mode. So, do the generic initialization, then reset
- * the page table cache mode to B=1,C=1, and note that
- * the PTEs need to be sync'd.
- */
- pmap_pte_init_generic();
-
- pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
- pte_l2_l_cache_mode_pt = L2_B|L2_C;
- pte_l2_s_cache_mode_pt = L2_B|L2_C;
-
- pmap_needs_pte_sync = 1;
-}
-#endif /* ARM_MMU_SA1 == 1*/
-
#if ARM_MMU_XSCALE == 1
#if (ARM_NMMUS > 1)
u_int xscale_use_minidata;
diff --git sys/arch/arm/armv7/bus_space_asm_armv7.S
sys/arch/arm/armv7/bus_space_asm_armv7.S
index 794f3a7..1461bdf 100644
--- sys/arch/arm/armv7/bus_space_asm_armv7.S
+++ sys/arch/arm/armv7/bus_space_asm_armv7.S
@@ -51,7 +51,7 @@ ENTRY(armv7_bs_r_1)
ldrb r0, [r1, r2]
mov pc, lr
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
+#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
ENTRY(armv7_bs_r_2)
dsb sy
ldrh r0, [r1, r2]
diff --git sys/arch/arm/conf/files.arm sys/arch/arm/conf/files.arm
index fefb206b..fd9d508 100644
--- sys/arch/arm/conf/files.arm
+++ sys/arch/arm/conf/files.arm
@@ -41,10 +41,6 @@ file arch/arm/arm/cpufunc.c
file arch/arm/arm/cpufunc_asm.S
file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9e | cpu_arm10 |
- cpu_sa110 |
- cpu_sa1100 |
- cpu_sa1110 |
- cpu_ixp12x0 |
cpu_xscale_80200 |
cpu_xscale_80321 |
cpu_xscale_ixp425 |
@@ -52,15 +48,10 @@ file arch/arm/arm/cpufunc_asm_armv4.S
cpu_arm9e | cpu_arm10 |
file arch/arm/arm/cpufunc_asm_armv5.S cpu_arm10
file arch/arm/arm/cpufunc_asm_armv5_ec.S cpu_arm9e | cpu_arm10
file arch/arm/arm/cpufunc_asm_armv7.S cpu_armv7
-file arch/arm/arm/cpufunc_asm_sa1.S cpu_sa110 | cpu_sa1100 |
- cpu_sa1110 |
- cpu_ixp12x0
-file arch/arm/arm/cpufunc_asm_sa11x0.S cpu_sa1100 | cpu_sa1110
file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 |
cpu_xscale_80321 |
cpu_xscale_ixp425 |
cpu_xscale_pxa2x0
-file arch/arm/arm/cpufunc_asm_ixp12x0.S cpu_ixp12x0
file arch/arm/arm/process_machdep.c
file arch/arm/arm/sig_machdep.c
file arch/arm/arm/sigcode.S
diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
index c5eb5e0..9c10aaa 100644
--- sys/arch/arm/include/armreg.h
+++ sys/arch/arm/include/armreg.h
@@ -185,10 +185,6 @@
#define CPU_ID_ARM1026EJS 0x4106a260
#define CPU_ID_ARM1136JS 0x4107b360
#define CPU_ID_ARM1136JSR1 0x4117b360
-#define CPU_ID_SA110 0x4401a100
-#define CPU_ID_SA1100 0x4401a110
-#define CPU_ID_SA1110 0x6901b110
-#define CPU_ID_IXP1200 0x6901c120
#define CPU_ID_80200 0x69052000
#define CPU_ID_PXA250 0x69052100 /* sans core revision */
#define CPU_ID_PXA210 0x69052120
diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
index caa0b46..2ce691c 100644
--- sys/arch/arm/include/cpuconf.h
+++ sys/arch/arm/include/cpuconf.h
@@ -48,13 +48,6 @@
/*
* Determine which ARM architecture versions are configured.
*/
-#if (defined(CPU_SA1100) || defined(CPU_SA1110) || \
- defined(CPU_IXP12X0))
-#define ARM_ARCH_4 1
-#else
-#define ARM_ARCH_4 0
-#endif
-
#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
@@ -80,9 +73,6 @@
*
* ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
*
- * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
- * ARM MMU, but has no write-through cache mode.
- *
* ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
* MMU, but also has several extensions which
* require different PTE layout to use.
@@ -97,13 +87,6 @@
#define ARM_MMU_GENERIC 0
#endif
-#if (defined(CPU_SA1100) || defined(CPU_SA1110) ||\
- defined(CPU_IXP12X0))
-#define ARM_MMU_SA1 1
-#else
-#define ARM_MMU_SA1 0
-#endif
-
#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
#define ARM_MMU_XSCALE 1
@@ -118,7 +101,7 @@
#endif
#define ARM_NMMUS (ARM_MMU_GENERIC + \
- ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V7)
+ ARM_MMU_XSCALE + ARM_MMU_V7)
/*
* Define features that may be present on a subset of CPUs
diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
index 0f3d65b..5ee569b 100644
--- sys/arch/arm/include/cpufunc.h
+++ sys/arch/arm/include/cpufunc.h
@@ -213,43 +213,6 @@ u_int cpufunc_dfar (void);
u_int cpufunc_ifsr (void);
u_int cpufunc_ifar (void);
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-void sa11x0_drain_readbuf (void);
-
-void sa11x0_context_switch (u_int);
-void sa11x0_cpu_sleep (int mode);
-
-void sa11x0_setup (void);
-#endif
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-void sa1_setttb (u_int ttb);
-
-void sa1_tlb_flushID_SE (u_int va);
-
-void sa1_cache_flushID (void);
-void sa1_cache_flushI (void);
-void sa1_cache_flushD (void);
-void sa1_cache_flushD_SE (u_int entry);
-
-void sa1_cache_cleanID (void);
-void sa1_cache_cleanD (void);
-void sa1_cache_cleanD_E (u_int entry);
-
-void sa1_cache_purgeID (void);
-void sa1_cache_purgeID_E (u_int entry);
-void sa1_cache_purgeD (void);
-void sa1_cache_purgeD_E (u_int entry);
-
-void sa1_cache_syncI (void);
-void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end);
-void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end);
-void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end);
-void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end);
-void sa1_cache_syncI_rng (vaddr_t start, vsize_t end);
-
-#endif
-
#if defined(CPU_ARM9E) || defined(CPU_ARM10)
void arm10_tlb_flushID_SE (u_int);
void arm10_tlb_flushI_SE (u_int);
@@ -352,7 +315,6 @@ extern unsigned armv7_dcache_index_inc;
#if defined(CPU_ARM9E) || defined(CPU_ARM10) || \
- defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
@@ -364,12 +326,6 @@ void armv4_tlb_flushD_SE (u_int va);
void armv4_drain_writebuf (void);
#endif
-#if defined(CPU_IXP12X0)
-void ixp12x0_drain_readbuf (void);
-void ixp12x0_context_switch (u_int);
-void ixp12x0_setup (void);
-#endif
-
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
(ARM_MMU_XSCALE == 1)
diff --git sys/arch/arm/include/pmap.h sys/arch/arm/include/pmap.h
index 93a5470..4603c2e 100644
--- sys/arch/arm/include/pmap.h
+++ sys/arch/arm/include/pmap.h
@@ -366,7 +366,7 @@ do {
\
/************************* ARM MMU configuration *****************************/
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0
+#if (ARM_MMU_GENERIC + ARM_MMU_V7) != 0
void pmap_copy_page_generic(struct vm_page *, struct vm_page *);
void pmap_zero_page_generic(struct vm_page *);
@@ -380,11 +380,7 @@ void pmap_pte_init_arm11(void);
#if defined(CPU_ARMv7)
void pmap_pte_init_armv7(void);
#endif /* CPU_ARMv7 */
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0 */
-
-#if ARM_MMU_SA1 == 1
-void pmap_pte_init_sa1(void);
-#endif /* ARM_MMU_SA1 == 1 */
+#endif /* (ARM_MMU_GENERIC + ARM_MMU_V7) != 0 */
#if ARM_MMU_V7 == 1
void pmap_pte_init_v7(void);
@@ -591,7 +587,7 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
#define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d))
#define pmap_zero_page(d) (*pmap_zero_page_func)((d))
-#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
+#elif ARM_MMU_GENERIC == 1
#define L1_S_PROT_UR L1_S_PROT_UR_generic
#define L1_S_PROT_UW L1_S_PROT_UW_generic
#define L1_S_PROT_KR L1_S_PROT_KR_generic
--
2.7.0
