On Sat, Mar 19, 2016 at 09:27:19AM +1100, Jonathan Gray wrote:
> On Fri, Mar 18, 2016 at 04:43:08PM +0100, Patrick Wildt wrote:
> > Hi,
> >
> > next up on the list is the StrongARM and IXP12x0.
> >
> > This diff removes most, but keeps the SA1100 headers,
> > which are still used by zaurus.
> >
> > Patrick
>
> Here is the diff I had:
>
> The only difference seems to be you've gone with
>
> #elif ARM_MMU_GENERIC == 1
>
> and I kept the != 0
>
> #elif (ARM_MMU_GENERIC) != 0
Yeah, I changed that to == 1 as there are no further calculations going
on anymore. As long as one of the versions goes in I'm happy.
>
> Index: arm/bus_space_asm_generic.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/bus_space_asm_generic.S,v
> retrieving revision 1.2
> diff -u -p -r1.2 bus_space_asm_generic.S
> --- arm/bus_space_asm_generic.S 8 May 2009 02:57:31 -0000 1.2
> +++ arm/bus_space_asm_generic.S 18 Mar 2016 22:17:19 -0000
> @@ -50,7 +50,7 @@ ENTRY(generic_bs_r_1)
> ldrb r0, [r1, r2]
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_r_2)
> ldrh r0, [r1, r2]
> mov pc, lr
> @@ -68,7 +68,7 @@ ENTRY(generic_bs_w_1)
> strb r3, [r1, r2]
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_w_2)
> strh r3, [r1, r2]
> mov pc, lr
> @@ -96,7 +96,7 @@ ENTRY(generic_bs_rm_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_rm_2)
> add r0, r1, r2
> mov r1, r3
> @@ -144,7 +144,7 @@ ENTRY(generic_bs_wm_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_wm_2)
> add r0, r1, r2
> mov r1, r3
> @@ -192,7 +192,7 @@ ENTRY(generic_bs_rr_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_rr_2)
> add r0, r1, r2
> mov r1, r3
> @@ -240,7 +240,7 @@ ENTRY(generic_bs_wr_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_wr_2)
> add r0, r1, r2
> mov r1, r3
> @@ -287,7 +287,7 @@ ENTRY(generic_bs_sr_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_sr_2)
> add r0, r1, r2
> mov r1, r3
> @@ -319,7 +319,7 @@ ENTRY(generic_bs_sr_4)
> * copy region
> */
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_c_2)
> add r0, r1, r2
> ldr r2, [sp, #0]
> Index: arm/cpu.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpu.c,v
> retrieving revision 1.24
> diff -u -p -r1.24 cpu.c
> --- arm/cpu.c 18 Mar 2016 13:16:02 -0000 1.24
> +++ arm/cpu.c 18 Mar 2016 22:17:20 -0000
> @@ -87,7 +87,6 @@ enum cpu_class {
> CPU_CLASS_ARM9ES,
> CPU_CLASS_ARM9EJS,
> CPU_CLASS_ARM10E,
> - CPU_CLASS_SA1,
> CPU_CLASS_XSCALE,
> CPU_CLASS_ARM11J,
> CPU_CLASS_ARMv7
> @@ -100,36 +99,6 @@ static const char * const generic_steppi
> "rev 12", "rev 13", "rev 14", "rev 15"
> };
>
> -static const char * const sa110_steppings[16] = {
> - "rev 0", "step J", "step K", "step S",
> - "step T", "rev 5", "rev 6", "rev 7",
> - "rev 8", "rev 9", "rev 10", "rev 11",
> - "rev 12", "rev 13", "rev 14", "rev 15"
> -};
> -
> -static const char * const sa1100_steppings[16] = {
> - "rev 0", "step B", "step C", "rev 3",
> - "rev 4", "rev 5", "rev 6", "rev 7",
> - "step D", "step E", "rev 10" "step G",
> - "rev 12", "rev 13", "rev 14", "rev 15"
> -};
> -
> -static const char * const sa1110_steppings[16] = {
> - "step A-0", "rev 1", "rev 2", "rev 3",
> - "step B-0", "step B-1", "step B-2", "step B-3",
> - "step B-4", "step B-5", "rev 10", "rev 11",
> - "rev 12", "rev 13", "rev 14", "rev 15"
> -};
> -
> -static const char * const ixp12x0_steppings[16] = {
> - "(IXP1200 step A)", "(IXP1200 step B)",
> - "rev 2", "(IXP1200 step C)",
> - "(IXP1200 step D)", "(IXP1240/1250 step A)",
> - "(IXP1240 step B)", "(IXP1250 step B)",
> - "rev 8", "rev 9", "rev 10", "rev 11",
> - "rev 12", "rev 13", "rev 14", "rev 15"
> -};
> -
> static const char * const xscale_steppings[16] = {
> "step A-0", "step A-1", "step B-0", "step C-0",
> "step D-0", "rev 5", "rev 6", "rev 7",
> @@ -206,16 +175,6 @@ const struct cpuidtab cpuids[] = {
> { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
> generic_steppings },
>
> - { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
> - sa110_steppings },
> - { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
> - sa1100_steppings },
> - { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110",
> - sa1110_steppings },
> -
> - { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200",
> - ixp12x0_steppings },
> -
> { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200",
> xscale_steppings },
>
> @@ -323,7 +282,6 @@ const struct cpu_classtab cpu_classes[]
> { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
> { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
> { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
> - { "SA-1", "CPU_SA1100" }, /* CPU_CLASS_SA1 */
> { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
> { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
> { "ARMv7", "CPU_ARMv7" } /* CPU_CLASS_ARMv7 */
> @@ -392,7 +350,6 @@ identify_arm_cpu(struct device *dv, stru
> case CPU_CLASS_ARM9ES:
> case CPU_CLASS_ARM9EJS:
> case CPU_CLASS_ARM10E:
> - case CPU_CLASS_SA1:
> case CPU_CLASS_XSCALE:
> case CPU_CLASS_ARM11J:
> case CPU_CLASS_ARMv7:
> @@ -457,9 +414,6 @@ identify_arm_cpu(struct device *dv, stru
> case CPU_CLASS_ARMv7:
> #endif
>
> -#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
> - case CPU_CLASS_SA1:
> -#endif
> #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
> defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
> case CPU_CLASS_XSCALE:
> Index: arm/cpufunc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpufunc.c,v
> retrieving revision 1.30
> diff -u -p -r1.30 cpufunc.c
> --- arm/cpufunc.c 18 Mar 2016 13:16:02 -0000 1.30
> +++ arm/cpufunc.c 18 Mar 2016 22:17:20 -0000
> @@ -327,121 +327,6 @@ struct cpu_functions armv7_cpufuncs = {
> };
> #endif /* CPU_ARMv7 */
>
> -
> -#if defined(CPU_SA1100) || defined(CPU_SA1110)
> -struct cpu_functions sa11x0_cpufuncs = {
> - /* CPU functions */
> -
> - cpufunc_id, /* id */
> - cpufunc_nullop, /* cpwait */
> -
> - /* MMU functions */
> -
> - cpufunc_control, /* control */
> - cpufunc_domains, /* domain */
> - sa1_setttb, /* setttb */
> - cpufunc_dfsr, /* dfsr */
> - cpufunc_dfar, /* dfar */
> - cpufunc_ifsr, /* ifsr */
> - cpufunc_ifar, /* ifar */
> -
> - /* TLB functions */
> -
> - armv4_tlb_flushID, /* tlb_flushID */
> - sa1_tlb_flushID_SE, /* tlb_flushID_SE */
> - armv4_tlb_flushI, /* tlb_flushI */
> - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
> - armv4_tlb_flushD, /* tlb_flushD */
> - armv4_tlb_flushD_SE, /* tlb_flushD_SE */
> -
> - /* Cache operations */
> -
> - sa1_cache_syncI, /* icache_sync_all */
> - sa1_cache_syncI_rng, /* icache_sync_range */
> -
> - sa1_cache_purgeD, /* dcache_wbinv_all */
> - sa1_cache_purgeD_rng, /* dcache_wbinv_range */
> -/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
> - sa1_cache_cleanD_rng, /* dcache_wb_range */
> -
> - sa1_cache_purgeID, /* idcache_wbinv_all */
> - sa1_cache_purgeID_rng, /* idcache_wbinv_range */
> -
> - cpufunc_nullop, /* sdcache_wbinv_all */
> - (void *)cpufunc_nullop, /* sdcache_wbinv_range */
> - (void *)cpufunc_nullop, /* sdcache_inv_range */
> - (void *)cpufunc_nullop, /* sdcache_wb_range */
> -
> - /* Other functions */
> -
> - sa11x0_drain_readbuf, /* flush_prefetchbuf */
> - armv4_drain_writebuf, /* drain_writebuf */
> -
> - sa11x0_cpu_sleep, /* sleep */
> -
> - /* Soft functions */
> - sa11x0_context_switch, /* context_switch */
> - sa11x0_setup /* cpu setup */
> -};
> -#endif /* CPU_SA1100 || CPU_SA1110 */
> -
> -#ifdef CPU_IXP12X0
> -struct cpu_functions ixp12x0_cpufuncs = {
> - /* CPU functions */
> -
> - cpufunc_id, /* id */
> - cpufunc_nullop, /* cpwait */
> -
> - /* MMU functions */
> -
> - cpufunc_control, /* control */
> - cpufunc_domains, /* domain */
> - sa1_setttb, /* setttb */
> - cpufunc_dfsr, /* dfsr */
> - cpufunc_dfar, /* dfar */
> - cpufunc_ifsr, /* ifsr */
> - cpufunc_ifar, /* ifar */
> -
> - /* TLB functions */
> -
> - armv4_tlb_flushID, /* tlb_flushID */
> - sa1_tlb_flushID_SE, /* tlb_flushID_SE */
> - armv4_tlb_flushI, /* tlb_flushI */
> - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
> - armv4_tlb_flushD, /* tlb_flushD */
> - armv4_tlb_flushD_SE, /* tlb_flushD_SE */
> -
> - /* Cache operations */
> -
> - sa1_cache_syncI, /* icache_sync_all */
> - sa1_cache_syncI_rng, /* icache_sync_range */
> -
> - sa1_cache_purgeD, /* dcache_wbinv_all */
> - sa1_cache_purgeD_rng, /* dcache_wbinv_range */
> -/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
> - sa1_cache_cleanD_rng, /* dcache_wb_range */
> -
> - sa1_cache_purgeID, /* idcache_wbinv_all */
> - sa1_cache_purgeID_rng, /* idcache_wbinv_range */
> -
> - cpufunc_nullop, /* sdcache_wbinv_all */
> - (void *)cpufunc_nullop, /* sdcache_wbinv_range */
> - (void *)cpufunc_nullop, /* sdcache_inv_range */
> - (void *)cpufunc_nullop, /* sdcache_wb_range */
> -
> - /* Other functions */
> -
> - ixp12x0_drain_readbuf, /* flush_prefetchbuf */
> - armv4_drain_writebuf, /* drain_writebuf */
> -
> - (void *)cpufunc_nullop, /* sleep */
> -
> - /* Soft functions */
> - ixp12x0_context_switch, /* context_switch */
> - ixp12x0_setup /* cpu setup */
> -};
> -#endif /* CPU_IXP12X0 */
> -
> #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
> defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
> struct cpu_functions xscale_cpufuncs = {
> @@ -590,58 +475,6 @@ get_cachetype_cp15()
> }
> #endif /* ARM7TDMI || ARM9 || XSCALE */
>
> -#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
> -/* Cache information for CPUs without cache type registers. */
> -struct cachetab {
> - u_int32_t ct_cpuid;
> - int ct_pcache_type;
> - int ct_pcache_unified;
> - int ct_pdcache_size;
> - int ct_pdcache_line_size;
> - int ct_pdcache_ways;
> - int ct_picache_size;
> - int ct_picache_line_size;
> - int ct_picache_ways;
> -};
> -
> -struct cachetab cachetab[] = {
> - /* cpuid, cache type, u, dsiz, ls, wy, isiz, ls,
> wy */
> - /* XXX is this type right for SA-1? */
> - { CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
> - { CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
> - { CPU_ID_IXP1200, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32,
> 32 }, /* XXX */
> - { 0, 0, 0, 0, 0, 0, 0, 0}
> -};
> -
> -static void get_cachetype_table (void);
> -
> -static void
> -get_cachetype_table()
> -{
> - int i;
> - u_int32_t cpuid = cpufunc_id();
> -
> - for (i = 0; cachetab[i].ct_cpuid != 0; i++) {
> - if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) {
> - arm_pcache_type = cachetab[i].ct_pcache_type;
> - arm_pcache_unified = cachetab[i].ct_pcache_unified;
> - arm_pdcache_size = cachetab[i].ct_pdcache_size;
> - arm_pdcache_line_size =
> - cachetab[i].ct_pdcache_line_size;
> - arm_pdcache_ways = cachetab[i].ct_pdcache_ways;
> - arm_picache_size = cachetab[i].ct_picache_size;
> - arm_picache_line_size =
> - cachetab[i].ct_picache_line_size;
> - arm_picache_ways = cachetab[i].ct_picache_ways;
> - }
> - }
> - arm_dcache_align = arm_pdcache_line_size;
> -
> - arm_dcache_align_mask = arm_dcache_align - 1;
> -}
> -
> -#endif /* SA110 || SA1100 || SA1111 || IXP12X0 */
> -
> #ifdef CPU_ARMv7
> void arm_get_cachetype_cp15v7 (void);
> int arm_dcache_l2_nsets;
> @@ -880,41 +713,6 @@ set_cpufuncs()
> return 0;
> }
> #endif /* CPU_ARMv7 */
> -#ifdef CPU_SA1100
> - if (cputype == CPU_ID_SA1100) {
> - cpufuncs = sa11x0_cpufuncs;
> - cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
> - get_cachetype_table();
> - pmap_pte_init_sa1();
> -
> - /* Use powersave on this CPU. */
> - cpu_do_powersave = 1;
> -
> - return 0;
> - }
> -#endif /* CPU_SA1100 */
> -#ifdef CPU_SA1110
> - if (cputype == CPU_ID_SA1110) {
> - cpufuncs = sa11x0_cpufuncs;
> - cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
> - get_cachetype_table();
> - pmap_pte_init_sa1();
> -
> - /* Use powersave on this CPU. */
> - cpu_do_powersave = 1;
> -
> - return 0;
> - }
> -#endif /* CPU_SA1110 */
> -#ifdef CPU_IXP12X0
> - if (cputype == CPU_ID_IXP1200) {
> - cpufuncs = ixp12x0_cpufuncs;
> - cpu_reset_needs_v4_MMU_disable = 1;
> - get_cachetype_table();
> - pmap_pte_init_sa1();
> - return 0;
> - }
> -#endif /* CPU_IXP12X0 */
> #ifdef CPU_XSCALE_80200
> if (cputype == CPU_ID_80200) {
> int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
> @@ -1167,65 +965,6 @@ armv7_setup()
> cpu_idcache_wbinv_all();
> }
> #endif /* CPU_ARMv7 */
> -
> -#if defined(CPU_SA1100) || defined(CPU_SA1110)
> -void
> -sa11x0_setup()
> -{
> - int cpuctrl, cpuctrlmask;
> -
> - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
> - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
> - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
> - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
> - | CPU_CONTROL_AFLT_ENABLE;
> - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
> - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
> - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
> - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
> - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
> - | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
> - | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
> -
> - if (vector_page == ARM_VECTORS_HIGH)
> - cpuctrl |= CPU_CONTROL_VECRELOC;
> -
> - /* Clear out the cache */
> - cpu_idcache_wbinv_all();
> -
> - /* Set the control register */
> - cpu_control(0xffffffff, cpuctrl);
> -}
> -#endif /* CPU_SA1100 || CPU_SA1110 */
> -
> -#if defined(CPU_IXP12X0)
> -void
> -ixp12x0_setup()
> -{
> - int cpuctrl, cpuctrlmask;
> -
> -
> - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE
> - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE
> - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_AFLT_ENABLE;
> - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE
> - | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE
> - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_SYST_ENABLE
> - | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE
> - | CPU_CONTROL_VECRELOC;
> -
> - if (vector_page == ARM_VECTORS_HIGH)
> - cpuctrl |= CPU_CONTROL_VECRELOC;
> -
> - /* Clear out the cache */
> - cpu_idcache_wbinv_all();
> -
> - /* Set the control register */
> - curcpu()->ci_ctrl = cpuctrl;
> - /* cpu_control(0xffffffff, cpuctrl); */
> - cpu_control(cpuctrlmask, cpuctrl);
> -}
> -#endif /* CPU_IXP12X0 */
>
> #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
> defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
> Index: arm/pmap.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/pmap.c,v
> retrieving revision 1.60
> diff -u -p -r1.60 pmap.c
> --- arm/pmap.c 18 Mar 2016 13:16:02 -0000 1.60
> +++ arm/pmap.c 18 Mar 2016 22:17:21 -0000
> @@ -3045,7 +3045,7 @@ pmap_reference(pmap_t pm)
> * StrongARM accesses to non-cached pages are non-burst making writing
> * _any_ bulk data very slow.
> */
> -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
> +#if (ARM_MMU_GENERIC) != 0
> void
> pmap_zero_page_generic(struct vm_page *pg)
> {
> @@ -3069,7 +3069,7 @@ pmap_zero_page_generic(struct vm_page *p
> bzero_page(cdstp);
> cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
> }
> -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
> +#endif /* (ARM_MMU_GENERIC) != 0 */
>
> #if ARM_MMU_XSCALE == 1
> void
> @@ -3105,7 +3105,7 @@ pmap_zero_page_xscale(struct vm_page *pg
> * hook points. The same comment regarding cachability as in
> * pmap_zero_page also applies here.
> */
> -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
> +#if (ARM_MMU_GENERIC) != 0
> void
> pmap_copy_page_generic(struct vm_page *src_pg, struct vm_page *dst_pg)
> {
> @@ -3144,7 +3144,7 @@ pmap_copy_page_generic(struct vm_page *s
> cpu_dcache_inv_range(csrcp, PAGE_SIZE);
> cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
> }
> -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
> +#endif /* (ARM_MMU_GENERIC) != 0 */
>
> #if ARM_MMU_XSCALE == 1
> void
> @@ -4380,7 +4380,7 @@ pt_entry_t pte_l2_s_proto;
> void (*pmap_copy_page_func)(struct vm_page *, struct vm_page *);
> void (*pmap_zero_page_func)(struct vm_page *);
>
> -#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
> +#if (ARM_MMU_GENERIC) != 0
> void
> pmap_pte_init_generic(void)
> {
> @@ -4438,7 +4438,7 @@ pmap_pte_init_generic(void)
> pmap_copy_page_func = pmap_copy_page_generic;
> pmap_zero_page_func = pmap_zero_page_generic;
> }
> -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
> +#endif /* (ARM_MMU_GENERIC) != 0 */
>
> #if defined(CPU_ARM10)
> void
> @@ -4545,27 +4545,6 @@ pmap_pte_init_armv7(void)
> pmap_needs_pte_sync = 1;
> }
> #endif /* CPU_ARMv7 */
> -
> -#if ARM_MMU_SA1 == 1
> -void
> -pmap_pte_init_sa1(void)
> -{
> -
> - /*
> - * The StrongARM SA-1 cache does not have a write-through
> - * mode. So, do the generic initialization, then reset
> - * the page table cache mode to B=1,C=1, and note that
> - * the PTEs need to be sync'd.
> - */
> - pmap_pte_init_generic();
> -
> - pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
> - pte_l2_l_cache_mode_pt = L2_B|L2_C;
> - pte_l2_s_cache_mode_pt = L2_B|L2_C;
> -
> - pmap_needs_pte_sync = 1;
> -}
> -#endif /* ARM_MMU_SA1 == 1*/
>
> #if ARM_MMU_XSCALE == 1
> #if (ARM_NMMUS > 1)
> Index: armv7/bus_space_asm_armv7.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/armv7/bus_space_asm_armv7.S,v
> retrieving revision 1.3
> diff -u -p -r1.3 bus_space_asm_armv7.S
> --- armv7/bus_space_asm_armv7.S 2 Jun 2015 02:30:16 -0000 1.3
> +++ armv7/bus_space_asm_armv7.S 18 Mar 2016 22:17:21 -0000
> @@ -51,7 +51,7 @@ ENTRY(armv7_bs_r_1)
> ldrb r0, [r1, r2]
> mov pc, lr
>
> -#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(armv7_bs_r_2)
> dsb sy
> ldrh r0, [r1, r2]
> Index: conf/files.arm
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/conf/files.arm,v
> retrieving revision 1.30
> diff -u -p -r1.30 files.arm
> --- conf/files.arm 18 Mar 2016 13:16:02 -0000 1.30
> +++ conf/files.arm 18 Mar 2016 22:17:21 -0000
> @@ -41,10 +41,6 @@ file arch/arm/arm/cpufunc.c
> file arch/arm/arm/cpufunc_asm.S
> file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
> file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9e | cpu_arm10 |
> - cpu_sa110 |
> - cpu_sa1100 |
> - cpu_sa1110 |
> - cpu_ixp12x0 |
> cpu_xscale_80200 |
> cpu_xscale_80321 |
> cpu_xscale_ixp425 |
> @@ -52,15 +48,10 @@ file arch/arm/arm/cpufunc_asm_armv4.S cp
> file arch/arm/arm/cpufunc_asm_armv5.S cpu_arm10
> file arch/arm/arm/cpufunc_asm_armv5_ec.S cpu_arm9e | cpu_arm10
> file arch/arm/arm/cpufunc_asm_armv7.S cpu_armv7
> -file arch/arm/arm/cpufunc_asm_sa1.S cpu_sa110 | cpu_sa1100 |
> - cpu_sa1110 |
> - cpu_ixp12x0
> -file arch/arm/arm/cpufunc_asm_sa11x0.S cpu_sa1100 | cpu_sa1110
> file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 |
> cpu_xscale_80321 |
> cpu_xscale_ixp425 |
> cpu_xscale_pxa2x0
> -file arch/arm/arm/cpufunc_asm_ixp12x0.S cpu_ixp12x0
> file arch/arm/arm/process_machdep.c
> file arch/arm/arm/sig_machdep.c
> file arch/arm/arm/sigcode.S
> Index: include/armreg.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/armreg.h,v
> retrieving revision 1.21
> diff -u -p -r1.21 armreg.h
> --- include/armreg.h 18 Mar 2016 13:16:02 -0000 1.21
> +++ include/armreg.h 18 Mar 2016 22:17:21 -0000
> @@ -185,10 +185,6 @@
> #define CPU_ID_ARM1026EJS 0x4106a260
> #define CPU_ID_ARM1136JS 0x4107b360
> #define CPU_ID_ARM1136JSR1 0x4117b360
> -#define CPU_ID_SA110 0x4401a100
> -#define CPU_ID_SA1100 0x4401a110
> -#define CPU_ID_SA1110 0x6901b110
> -#define CPU_ID_IXP1200 0x6901c120
> #define CPU_ID_80200 0x69052000
> #define CPU_ID_PXA250 0x69052100 /* sans core revision */
> #define CPU_ID_PXA210 0x69052120
> Index: include/cpuconf.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/cpuconf.h,v
> retrieving revision 1.10
> diff -u -p -r1.10 cpuconf.h
> --- include/cpuconf.h 18 Mar 2016 13:35:25 -0000 1.10
> +++ include/cpuconf.h 18 Mar 2016 22:17:21 -0000
> @@ -48,13 +48,6 @@
> /*
> * Determine which ARM architecture versions are configured.
> */
> -#if (defined(CPU_SA1100) || defined(CPU_SA1110) || \
> - defined(CPU_IXP12X0))
> -#define ARM_ARCH_4 1
> -#else
> -#define ARM_ARCH_4 0
> -#endif
> -
> #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
> defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||
> \
> defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
> @@ -80,9 +73,6 @@
> *
> * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
> *
> - * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
> - * ARM MMU, but has no write-through cache mode.
> - *
> * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
> * MMU, but also has several extensions which
> * require different PTE layout to use.
> @@ -97,13 +87,6 @@
> #define ARM_MMU_GENERIC 0
> #endif
>
> -#if (defined(CPU_SA1100) || defined(CPU_SA1110) ||\
> - defined(CPU_IXP12X0))
> -#define ARM_MMU_SA1 1
> -#else
> -#define ARM_MMU_SA1 0
> -#endif
> -
> #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||
> \
> defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
> #define ARM_MMU_XSCALE 1
> @@ -118,7 +101,7 @@
> #endif
>
> #define ARM_NMMUS (ARM_MMU_GENERIC + \
> - ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V7)
> + ARM_MMU_XSCALE + ARM_MMU_V7)
>
> /*
> * Define features that may be present on a subset of CPUs
> Index: include/cpufunc.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/cpufunc.h,v
> retrieving revision 1.18
> diff -u -p -r1.18 cpufunc.h
> --- include/cpufunc.h 18 Mar 2016 13:16:02 -0000 1.18
> +++ include/cpufunc.h 18 Mar 2016 22:17:21 -0000
> @@ -213,43 +213,6 @@ u_int cpufunc_dfar (void);
> u_int cpufunc_ifsr (void);
> u_int cpufunc_ifar (void);
>
> -#if defined(CPU_SA1100) || defined(CPU_SA1110)
> -void sa11x0_drain_readbuf (void);
> -
> -void sa11x0_context_switch (u_int);
> -void sa11x0_cpu_sleep (int mode);
> -
> -void sa11x0_setup (void);
> -#endif
> -
> -#if defined(CPU_SA1100) || defined(CPU_SA1110)
> -void sa1_setttb (u_int ttb);
> -
> -void sa1_tlb_flushID_SE (u_int va);
> -
> -void sa1_cache_flushID (void);
> -void sa1_cache_flushI (void);
> -void sa1_cache_flushD (void);
> -void sa1_cache_flushD_SE (u_int entry);
> -
> -void sa1_cache_cleanID (void);
> -void sa1_cache_cleanD (void);
> -void sa1_cache_cleanD_E (u_int entry);
> -
> -void sa1_cache_purgeID (void);
> -void sa1_cache_purgeID_E (u_int entry);
> -void sa1_cache_purgeD (void);
> -void sa1_cache_purgeD_E (u_int entry);
> -
> -void sa1_cache_syncI (void);
> -void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end);
> -void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end);
> -void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end);
> -void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end);
> -void sa1_cache_syncI_rng (vaddr_t start, vsize_t end);
> -
> -#endif
> -
> #if defined(CPU_ARM9E) || defined(CPU_ARM10)
> void arm10_tlb_flushID_SE (u_int);
> void arm10_tlb_flushI_SE (u_int);
> @@ -352,7 +315,6 @@ extern unsigned armv7_dcache_index_inc;
>
>
> #if defined(CPU_ARM9E) || defined(CPU_ARM10) || \
> - defined(CPU_SA1100) || defined(CPU_SA1110) || \
> defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
> defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
>
> @@ -362,12 +324,6 @@ void armv4_tlb_flushD (void);
> void armv4_tlb_flushD_SE (u_int va);
>
> void armv4_drain_writebuf (void);
> -#endif
> -
> -#if defined(CPU_IXP12X0)
> -void ixp12x0_drain_readbuf (void);
> -void ixp12x0_context_switch (u_int);
> -void ixp12x0_setup (void);
> #endif
>
> #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
> Index: include/pmap.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/pmap.h,v
> retrieving revision 1.37
> diff -u -p -r1.37 pmap.h
> --- include/pmap.h 18 Mar 2016 13:16:02 -0000 1.37
> +++ include/pmap.h 18 Mar 2016 22:17:21 -0000
> @@ -366,7 +366,7 @@ do {
> \
>
> /************************* ARM MMU configuration
> *****************************/
>
> -#if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0
> +#if (ARM_MMU_GENERIC + ARM_MMU_V7) != 0
> void pmap_copy_page_generic(struct vm_page *, struct vm_page *);
> void pmap_zero_page_generic(struct vm_page *);
>
> @@ -380,11 +380,7 @@ void pmap_pte_init_arm11(void);
> #if defined(CPU_ARMv7)
> void pmap_pte_init_armv7(void);
> #endif /* CPU_ARMv7 */
> -#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0 */
> -
> -#if ARM_MMU_SA1 == 1
> -void pmap_pte_init_sa1(void);
> -#endif /* ARM_MMU_SA1 == 1 */
> +#endif /* (ARM_MMU_GENERIC + ARM_MMU_V7) != 0 */
>
> #if ARM_MMU_V7 == 1
> void pmap_pte_init_v7(void);
> @@ -591,7 +587,7 @@ extern void (*pmap_zero_page_func)(struc
>
> #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d))
> #define pmap_zero_page(d) (*pmap_zero_page_func)((d))
> -#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
> +#elif (ARM_MMU_GENERIC) != 0
> #define L1_S_PROT_UR L1_S_PROT_UR_generic
> #define L1_S_PROT_UW L1_S_PROT_UW_generic
> #define L1_S_PROT_KR L1_S_PROT_KR_generic
>
