On Tue, Apr 12, 2016 at 05:03:39PM +0200, Mark Kettenis wrote: > > On Fri, Apr 08, 2016 at 12:16:03PM +0000, Visa Hankala wrote: > > > Every now and then I see "spurious interrupt 34" messages on octeon > > > serial console. The root cause seems to be in comstart() which enables > > > the TX holding register empty interrupt before writing data to the TX > > > register. If the register is empty initially, the early enabling can > > > trigger a premature interrupt. > > > > > > The message does not appear when the enabling is done after the data > > > writing. The change has not caused ill effects on amd64, i386 and sgi > > > machines that I used for testing. OK? > > > > Any objections to this patch? The timing issue is generic, not specific > > to octeon. > > Was going to check the hardware description of these registers. The > worry I have is that enabling the interrupt after pushing out the > character will make us miss completions. But that is not an issue if > the interrupt is latched.
It should be latched, at least on modern 16550-like UARTs. From a PC16550D datasheet: "When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows: 1. The transmitter holding register empty interrupt occurs when the transmit FIFO is empty. It is cleared when the THR is written to or the IIR is read. 2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled."
