On Tue, Jun 05, 2018 at 11:11:21AM +0200, Frederic Cambus wrote:
> Hi tech@,
>
> VIA C7 CPUs support Enhanced SpeedStep, so reflect that in cpu.4.
>
> On the VIA C7 1.5Ghz:
>
> cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.51 GHz
> cpu0:
> FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2
> cpu0: Enhanced SpeedStep 1501 MHz: speeds: 1500, 800 MHz
>
> Comments? OK?
If you just have the faked high/low table does it really support it
besides setting the cpuid bit? No PSS in ACPI? There is a table
for a 1.5GHz C7 in i386
/* 1.50GHz Centaur C7-M 400 MHz FSB */
static struct est_op C7M_754[] = {
ID16(1500, 1004, BUS100),
ID16(1400, 988, BUS100),
ID16(1000, 940, BUS100),
ID16( 800, 844, BUS100),
ID16( 600, 844, BUS100),
ID16( 400, 844, BUS100),
};
VIA seems to refer to changing the frequency on C7 as 'Enhanced PowerSaver'.
>
> Index: share/man/man4/man4.i386/cpu.4
> ===================================================================
> RCS file: /cvs/src/share/man/man4/man4.i386/cpu.4,v
> retrieving revision 1.18
> diff -u -p -r1.18 cpu.4
> --- share/man/man4/man4.i386/cpu.4 12 Jan 2018 04:36:44 -0000 1.18
> +++ share/man/man4/man4.i386/cpu.4 5 Jun 2018 08:39:38 -0000
> @@ -53,8 +53,8 @@ positions.
> The processor dynamically adjusts frequency in response to load; the setperf
> value is interpreted as the maximum.
> .It EST
> -Enhanced SpeedStep found on Intel Pentium M processors,
> -offering frequency scaling with numerous positions.
> +Enhanced SpeedStep found on Intel Pentium M and newer processors, as well as
> +on VIA C7 processors, offering frequency scaling with numerous positions.
> .It SpeedStep
> Found on some Intel Pentium 3 and newer mobile chips,
> it is capable of adjusting frequency between a low and high value.
>
