On Tue, Jun 05, 2018 at 10:04:52PM +1000, Jonathan Gray wrote:
> > VIA C7 CPUs support Enhanced SpeedStep, so reflect that in cpu.4.
> >
> > On the VIA C7 1.5Ghz:
> >
> > cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.51 GHz
> > cpu0:
> > FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2
> > cpu0: Enhanced SpeedStep 1501 MHz: speeds: 1500, 800 MHz
>
> If you just have the faked high/low table does it really support it
> besides setting the cpuid bit? No PSS in ACPI? There is a table
> for a 1.5GHz C7 in i386
>
> /* 1.50GHz Centaur C7-M 400 MHz FSB */
> static struct est_op C7M_754[] = {
> ID16(1500, 1004, BUS100),
> ID16(1400, 988, BUS100),
> ID16(1000, 940, BUS100),
> ID16( 800, 844, BUS100),
> ID16( 600, 844, BUS100),
> ID16( 400, 844, BUS100),
> };
Sorry for the delay, I wanted to try booting an old VIA C7 motherboard
I have (the dmesg bits from previous mail came from our dmesg archive)
before answering.
I finally was able to find it and do so, and indeed it seems there are
some issues as well:
cpu0: VIA C7 Processor 1000MHz ("CentaurHauls" 686-class) 1 GHz
cpu0:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACPI,MMX,FXSR,SSE,SSE2,TM,PBE,NXE,SSE3,EST,TM2,xTPR
cpu0: unknown Enhanced SpeedStep CPU, msr 0x08100a1308000a13
cpu0: using only highest and lowest power states
cpu0: Enhanced SpeedStep 998 MHz: speeds: 1333, 1067 MHz
I'm not sure it makes sense to spend any time on this, let's forget it.
