So regress/lib/libm/msun/run-conj_test fails because clang emits
fmovqne instructions. Those instructions aren't actually implemented
and since we don't emulate them in our kernel the test gets killed
with SIGILL.
The compiler isn't suppose to emit the instructions unless they are
explicitly enabled. The instruction tables contain a few mistakes.
In particular if predicates are set for a block of instruction
patterns the Requires<[HasHardQuad]> doesn't seem to do anything.
ok?
Index: gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td
===================================================================
RCS file: /cvs/src/gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td,v
retrieving revision 1.1.1.3
diff -u -p -r1.1.1.3 SparcInstr64Bit.td
--- gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td 23 Jun 2019 21:36:36
-0000 1.1.1.3
+++ gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td 4 Apr 2020 21:30:57
-0000
@@ -337,6 +337,7 @@ def FMOVD_XCC : F4_3<0b110101, 0b000010,
"fmovd$cond %xcc, $rs2, $rd",
[(set f64:$rd,
(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
+let Predicates = [Is64Bit, HasHardQuad] in
def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond %xcc, $rs2, $rd",
@@ -437,11 +438,11 @@ def FXTOD : F3_3u<2, 0b110100, 0b0100010
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fxtod $rs2, $rd",
[(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
+let Predicates = [Is64Bit, HasHardQuad] in
def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
(outs QFPRegs:$rd), (ins DFPRegs:$rs2),
"fxtoq $rs2, $rd",
- [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
def FSTOX : F3_3u<2, 0b110100, 0b010000001,
(outs DFPRegs:$rd), (ins FPRegs:$rs2),
@@ -451,11 +452,11 @@ def FDTOX : F3_3u<2, 0b110100, 0b0100000
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fdtox $rs2, $rd",
[(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>;
+let Predicates = [Is64Bit, HasHardQuad] in
def FQTOX : F3_3u<2, 0b110100, 0b010000011,
(outs DFPRegs:$rd), (ins QFPRegs:$rs2),
"fqtox $rs2, $rd",
- [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>;
} // Predicates = [Is64Bit]
Index: gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td
===================================================================
RCS file: /cvs/src/gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td,v
retrieving revision 1.1.1.7
diff -u -p -r1.1.1.7 SparcInstrInfo.td
--- gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td 23 Jun 2019 21:36:36 -0000
1.1.1.7
+++ gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td 4 Apr 2020 21:30:57 -0000
@@ -1392,12 +1392,12 @@ let Predicates = [HasV9], Constraints =
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond %icc, $rs2, $rd",
[(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FMOVQ_ICC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond %icc, $rs2, $rd",
- [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
}
let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
@@ -1411,12 +1411,12 @@ let Predicates = [HasV9], Constraints =
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond %fcc0, $rs2, $rd",
[(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FMOVQ_FCC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond %fcc0, $rs2, $rd",
- [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
}
}
@@ -1426,28 +1426,28 @@ let Predicates = [HasV9] in {
def FMOVD : F3_3u<2, 0b110100, 0b000000010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fmovd $rs2, $rd", []>;
+ let Predicates = [HasV9, HasHardQuad] in
def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
- "fmovq $rs2, $rd", []>,
- Requires<[HasHardQuad]>;
+ "fmovq $rs2, $rd", []>;
def FNEGD : F3_3u<2, 0b110100, 0b000000110,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fnegd $rs2, $rd",
[(set f64:$rd, (fneg f64:$rs2))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
"fnegq $rs2, $rd",
- [(set f128:$rd, (fneg f128:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (fneg f128:$rs2))]>;
def FABSD : F3_3u<2, 0b110100, 0b000001010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fabsd $rs2, $rd",
[(set f64:$rd, (fabs f64:$rs2))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FABSQ : F3_3u<2, 0b110100, 0b000001011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
"fabsq $rs2, $rd",
- [(set f128:$rd, (fabs f128:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (fabs f128:$rs2))]>;
}
// Floating-point compare instruction with %fcc0-%fcc3.
@@ -1494,11 +1494,11 @@ let Predicates = [HasV9] in {
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
(ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond $opf_cc, $rs2, $rd", []>;
+ let Predicates = [HasV9, HasHardQuad] in
def V9FMOVQ_FCC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
- "fmovq$cond $opf_cc, $rs2, $rd", []>,
- Requires<[HasHardQuad]>;
+ "fmovq$cond $opf_cc, $rs2, $rd", []>;
} // Constraints = "$f = $rd", ...
} // let Predicates = [hasV9]
