> Date: Sat, 4 Apr 2020 23:46:05 +0200 (CEST)
> From: Mark Kettenis <[email protected]>
>
> So regress/lib/libm/msun/run-conj_test fails because clang emits
> fmovqne instructions. Those instructions aren't actually implemented
> and since we don't emulate them in our kernel the test gets killed
> with SIGILL.
>
> The compiler isn't suppose to emit the instructions unless they are
> explicitly enabled. The instruction tables contain a few mistakes.
> In particular if predicates are set for a block of instruction
> patterns the Requires<[HasHardQuad]> doesn't seem to do anything.
>
> ok?
That diff didn't actually work. Seems we need to provide some
additional magic such that clang knows to use a conditional branch
instead to replace the conditional move.
ok?
Index: gnu/llvm/lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
RCS file: /cvs/src/gnu/llvm/lib/Target/Sparc/SparcISelLowering.cpp,v
retrieving revision 1.4
diff -u -p -r1.4 SparcISelLowering.cpp
--- gnu/llvm/lib/Target/Sparc/SparcISelLowering.cpp 23 Jun 2019 22:05:14
-0000 1.4
+++ gnu/llvm/lib/Target/Sparc/SparcISelLowering.cpp 5 Apr 2020 20:48:22
-0000
@@ -3103,6 +3103,11 @@ SparcTargetLowering::EmitInstrWithCustom
case SP::SELECT_CC_DFP_ICC:
case SP::SELECT_CC_QFP_ICC:
return expandSelectCC(MI, BB, SP::BCOND);
+ case SP::SELECT_CC_Int_XCC:
+ case SP::SELECT_CC_FP_XCC:
+ case SP::SELECT_CC_DFP_XCC:
+ case SP::SELECT_CC_QFP_XCC:
+ return expandSelectCC(MI, BB, SP::BPXCC);
case SP::SELECT_CC_Int_FCC:
case SP::SELECT_CC_FP_FCC:
case SP::SELECT_CC_DFP_FCC:
Index: gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td
===================================================================
RCS file: /cvs/src/gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td,v
retrieving revision 1.1.1.3
diff -u -p -r1.1.1.3 SparcInstr64Bit.td
--- gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td 23 Jun 2019 21:36:36
-0000 1.1.1.3
+++ gnu/llvm/lib/Target/Sparc/SparcInstr64Bit.td 5 Apr 2020 20:48:22
-0000
@@ -337,6 +337,7 @@ def FMOVD_XCC : F4_3<0b110101, 0b000010,
"fmovd$cond %xcc, $rs2, $rd",
[(set f64:$rd,
(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
+let Predicates = [Is64Bit, HasHardQuad] in
def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond %xcc, $rs2, $rd",
@@ -437,11 +438,11 @@ def FXTOD : F3_3u<2, 0b110100, 0b0100010
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fxtod $rs2, $rd",
[(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
+let Predicates = [Is64Bit, HasHardQuad] in
def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
(outs QFPRegs:$rd), (ins DFPRegs:$rs2),
"fxtoq $rs2, $rd",
- [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
def FSTOX : F3_3u<2, 0b110100, 0b010000001,
(outs DFPRegs:$rd), (ins FPRegs:$rs2),
@@ -451,11 +452,11 @@ def FDTOX : F3_3u<2, 0b110100, 0b0100000
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fdtox $rs2, $rd",
[(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>;
+let Predicates = [Is64Bit, HasHardQuad] in
def FQTOX : F3_3u<2, 0b110100, 0b010000011,
(outs DFPRegs:$rd), (ins QFPRegs:$rs2),
"fqtox $rs2, $rd",
- [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>;
} // Predicates = [Is64Bit]
Index: gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td
===================================================================
RCS file: /cvs/src/gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td,v
retrieving revision 1.1.1.7
diff -u -p -r1.1.1.7 SparcInstrInfo.td
--- gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td 23 Jun 2019 21:36:36 -0000
1.1.1.7
+++ gnu/llvm/lib/Target/Sparc/SparcInstrInfo.td 5 Apr 2020 20:48:22 -0000
@@ -469,6 +469,27 @@ let Uses = [ICC], usesCustomInserter = 1
[(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
}
+let Uses = [ICC], usesCustomInserter = 1 in {
+ def SELECT_CC_Int_XCC
+ : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_Int_XCC PSEUDO!",
+ [(set i32:$dst, (SPselectxcc i32:$T, i32:$F, imm:$Cond))]>;
+ def SELECT_CC_FP_XCC
+ : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_FP_XCC PSEUDO!",
+ [(set f32:$dst, (SPselectxcc f32:$T, f32:$F, imm:$Cond))]>;
+
+ def SELECT_CC_DFP_XCC
+ : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_DFP_XCC PSEUDO!",
+ [(set f64:$dst, (SPselectxcc f64:$T, f64:$F, imm:$Cond))]>;
+
+ def SELECT_CC_QFP_XCC
+ : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_QFP_XCC PSEUDO!",
+ [(set f128:$dst, (SPselectxcc f128:$T, f128:$F, imm:$Cond))]>;
+}
+
let usesCustomInserter = 1, Uses = [FCC0] in {
def SELECT_CC_Int_FCC
@@ -1392,12 +1413,12 @@ let Predicates = [HasV9], Constraints =
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond %icc, $rs2, $rd",
[(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FMOVQ_ICC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond %icc, $rs2, $rd",
- [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
}
let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
@@ -1411,12 +1432,12 @@ let Predicates = [HasV9], Constraints =
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond %fcc0, $rs2, $rd",
[(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FMOVQ_FCC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovq$cond %fcc0, $rs2, $rd",
- [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
}
}
@@ -1426,28 +1447,28 @@ let Predicates = [HasV9] in {
def FMOVD : F3_3u<2, 0b110100, 0b000000010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fmovd $rs2, $rd", []>;
+ let Predicates = [HasV9, HasHardQuad] in
def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
- "fmovq $rs2, $rd", []>,
- Requires<[HasHardQuad]>;
+ "fmovq $rs2, $rd", []>;
def FNEGD : F3_3u<2, 0b110100, 0b000000110,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fnegd $rs2, $rd",
[(set f64:$rd, (fneg f64:$rs2))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
"fnegq $rs2, $rd",
- [(set f128:$rd, (fneg f128:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (fneg f128:$rs2))]>;
def FABSD : F3_3u<2, 0b110100, 0b000001010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fabsd $rs2, $rd",
[(set f64:$rd, (fabs f64:$rs2))]>;
+ let Predicates = [HasV9, HasHardQuad] in
def FABSQ : F3_3u<2, 0b110100, 0b000001011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2),
"fabsq $rs2, $rd",
- [(set f128:$rd, (fabs f128:$rs2))]>,
- Requires<[HasHardQuad]>;
+ [(set f128:$rd, (fabs f128:$rs2))]>;
}
// Floating-point compare instruction with %fcc0-%fcc3.
@@ -1494,11 +1515,11 @@ let Predicates = [HasV9] in {
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
(ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond $opf_cc, $rs2, $rd", []>;
+ let Predicates = [HasV9, HasHardQuad] in
def V9FMOVQ_FCC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
- "fmovq$cond $opf_cc, $rs2, $rd", []>,
- Requires<[HasHardQuad]>;
+ "fmovq$cond $opf_cc, $rs2, $rd", []>;
} // Constraints = "$f = $rd", ...
} // let Predicates = [hasV9]
