Scott Cheloha <scottchel...@gmail.com> [2022-09-23, 09:16 -0500]:
> Hi,
>
> TL;DR:
>
> I want to compute the TSC frequency on AMD CPUs using the methods laid
> out in the AMD manuals instead of calibrating the TSC by hand.
>
> If you have an AMD CPU with an invariant TSC, please apply this patch,
> recompile/boot the resulting kernel, and send me the resulting dmesg.
>
> Family 10h-16h CPUs are especially interesting. If you've got one,
> don't be shy!
>
> Long explanation:
>
> On AMD CPUs we calibrate the TSC with a separate timer. This is slow
> and introduces error. I also worry about a future where legacy timers
> are absent or heavily gated (read: useless).
>
> This patch adds most of the code needed to compute the TSC frequency
> on AMD family 10h+ CPUs. CPUs prior to family 10h did not support an
> invariant TSC so they are irrelevant.
>
> I have riddled the code with printf(9) calls so I can work out what's
> wrong by hand if a test result makes no sense.
>
> The only missing piece is code to read the configuration space on
> family 10h-16h CPUs to determine how many boosted P-states we need to
> skip to get to the MSR describing the software P0 state. I would
> really appreciate it if someone could explain how to do this at this
> very early point in boot. jsg@ pointed me to pci_conf_read(9), but
> I'm a little confused about how I get the needed pci* inputs at this
> point in boot.
>
> --
>
> Test results? Clues on reading the configuration space?
>
> -Scott
>
> Index: tsc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
> retrieving revision 1.29
> diff -u -p -r1.29 tsc.c
> --- tsc.c 22 Sep 2022 04:57:08 -0000 1.29
> +++ tsc.c 23 Sep 2022 14:04:22 -0000
> @@ -100,6 +100,253 @@ tsc_freq_cpuid(struct cpu_info *ci)
> return (0);
> }
>
> +uint64_t
> +tsc_freq_msr(struct cpu_info *ci)
> +{
> + uint64_t base, def, did, did_lsd, did_msd, divisor, fid, multiplier;
> + uint32_t msr, off = 0;
> +
> + if (strcmp(cpu_vendor, "AuthenticAMD") != 0)
> + return 0;
> +
> + /*
> + * All family 10h+ CPUs have MSR_HWCR and the TscFreqSel bit.
> + * If TscFreqSel is not set the TSC does not advance at the P0
> + * frequency, in which case something is wrong and we need to
> + * calibrate by hand.
> + */
> +#define HWCR_TSCFREQSEL (1 << 24)
> + if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL)) /* XXX specialreg.h */
> + return 0;
> +#undef HWCR_TSCFREQSEL
> +
> + /*
> + * For families 10h, 12h, 14h, 15h, and 16h, we need to skip past
> + * the boosted P-states (Pb0, Pb1, etc.) to find the MSR describing
> + * P0, i.e. the highest performance unboosted P-state. The number
> + * of boosted states is kept in the "Core Performance Boost Control"
> + * configuration space register.
> + */
> +#ifdef __not_yet__
> + uint32_t reg;
> + switch (ci->ci_family) {
> + case 0x10:
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(F4x15C);
> + off = (reg >> 2) & 0x1;
> + break;
> + case 0x12:
> + case 0x14:
> + case 0x15:
> + case 0x16:
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(D18F4x15C);
> + off = (reg >> 2) & 0x7;
> + break;
> + default:
> + break;
> + }
> +#endif
> +
> +/* DEBUG Let's look at all the MSRs to check my math. */
> +for (; off < 8; off++) {
> +
> + /*
> + * In family 10h+, core P-state voltage/frequency definitions
> + * are kept in MSRs C001_006[4:B] (eight registers in total).
> + * All MSRs in the range are readable, but if the EN bit isn't
> + * set the register doesn't define a valid P-state.
> + */
> + msr = 0xc0010064 + off; /* XXX specialreg.h */
> + def = rdmsr(msr);
> + printf("%s: MSR %04X_%04X: en %d",
> + ci->ci_dev->dv_xname, msr >> 16, msr & 0xffff,
> + !!ISSET(def, 1ULL << 63));
> + if (!ISSET(def, 1ULL << 63)) { /* XXX specialreg.h */
> + printf("\n");
> + continue;
> + }
> + switch (ci->ci_family) {
> + case 0x10:
> + /* AMD Family 10h Processor BKDG, Rev 3.62, p. 429 */
> + base = 100000000; /* 100.0 MHz */
> + did = (def >> 6) & 0x7;
> + divisor = 1ULL << did;
> + fid = def & 0x1f;
> + multiplier = fid + 0x10;
> + printf(" base %llu did %llu div %llu fid %llu mul %llu",
> + base, did, divisor, fid, multiplier);
> + break;
> + case 0x11:
> + /* AMD Family 11h Processor BKDG, Rev 3.62, p. 236 */
> + base = 100000000; /* 100.0 MHz */
> + did = (def >> 6) & 0x7;
> + divisor = 1ULL << did;
> + fid = def & 0x1f;
> + multiplier = fid + 0x8;
> + printf(" base %llu did %llu div %llu fid %llu mul %llu",
> + base, did, divisor, fid, multiplier);
> + break;
> + case 0x12:
> + /* AMD Family 12h Processor BKDG, Rev 3.02, pp. 468-469 */
> + base = 100000000; /* 100.0 MHz */
> + fid = (def >> 4) & 0xf;
> + multiplier = fid + 0x10;
> +
> + /*
> + * A CpuDid of 1 maps to a divisor of 1.5. To simulate
> + * this with integer math we use a divisor of 3 and double
> + * the multiplier, as (X * 2 / 3) equals (X / 1.5). All
> + * other CpuDid values map to to whole number divisors
> + * or are reserved.
> + */
> + did = def & 0xf;
> + printf(" did %llu", did);
> + if (did >= 8) {
> + printf("(reserved)\n");
> + continue; /* reserved */
> + }
> + if (did == 1)
> + multiplier *= 2;
> + uint64_t did_divisor[] = { 1, 3, 2, 3, 4, 6, 8, 12, 16 };
> + divisor = did_divisor[did];
> + printf(" div %llu base %llu fid %llu mul %llu",
> + divisor, base, fid, multiplier);
> + break;
> + case 0x14:
> + /*
> + * BKDG for AMD Family 14h Models 00h-0Fh Processors,
> + * Rev 3.13, pp. 428-429
> + *
> + * Family 14h doesn't have CpuFid or CpuDid. Instead,
> + * the CpuCOF divisor is derived from two new fields:
> + * CpuDidMsd, the integral base, and CpuDidLsd, the
> + * fractional multiplier. The formula for the divisor
> + * varies with the magnitude of CpuDidMsd:
> + *
> + * CpuDidMsd <= 14: CpuDidMsd + 1 + (CpuDidLsd * 0.25)
> + * CpuDidMsd >= 15: CpuDidMsd + 1 + ((CpuDidLsd & 0x10) * 0.25)
> + *
> + * CpuCOF is just (base / divisor), however we need to
> + * multiply both sides by 100 to simulate fractional
> + * division with integer math, e.g. (X * 100 / 125) is
> + * equivalent to (X / 1.25).
> + */
> +#if __not_yet__
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(D18F3xD4);
> + base = 100000000 * ((reg & 0x3f) + 0x10);
> +#else
> + base = 100000000; /* XXX guess 100.0 MHz for now... */
> +#endif
> + multiplier = 100;
> + did_msd = (def >> 4) & 0x19;
> + printf(" msd %llu", did_msd);
> + if (did_msd >= 27) {
> + printf("(reserved)\n");
> + continue; /* XXX might be reserved? */
> + }
> + did_lsd = def & 0xf;
> + printf(" lsd %llu", did_lsd);
> + if (did_lsd >= 4) {
> + printf("(reserved)\n");
> + continue; /* reserved */
> + }
> + if (did_msd >= 15)
> + did_lsd &= 0x10;
> + divisor = (did_msd + 1) * 100 + (did_lsd * 25);
> + printf(" div %llu base %llu mul %llu",
> + divisor, base, multiplier);
> + break;
> + case 0x15:
> + /*
> + * BKDG for AMD Family 15h [...]:
> + * Models 00h-OFh Processors, Rev 3.14, pp. 569-571
> + * Models 10h-1Fh Processors, Rev 3.12, pp. 580-581
> + * Models 30h-3Fh Processors, Rev 3.06, pp. 634-636
> + * Models 60h-6Fh Processors, Rev 3.05, pp. 691-693
> + * Models 70h-7Fh Processors, Rev 3.09, pp. 655-656
> + */
> + base = 100000000; /* 100.0 Mhz */
> + did = (def >> 6) & 0x7;
> + printf(" base %llu did %llu", base, did);
> + if (did >= 0x5) {
> + printf("(reserved)\n");
> + continue; /* reserved */
> + }
> + divisor = 1ULL << did;
> +
> + /*
> + * BKDG for AMD Family 15h Models 00h-0Fh, Rev 3.14, p. 571
> + * says that "CpuFid must be less than or equal to 2Fh."
> + * No other BKDG for family 15h limits the range of CpuFid.
> + */
> + fid = def & 0x3f;
> + printf(" fid %llu", fid);
> + if (ci->ci_model <= 0x0f && fid >= 0x30) {
> + printf("(reserved)\n");
> + continue; /* reserved */
> + }
> + multiplier = fid + 0x10;
> + printf(" mul %llu div %llu", multiplier, divisor);
> + break;
> + case 0x16:
> + /*
> + * BKDG for AMD Family 16h [...]:
> + * Models 00h-0Fh Processors, Rev 3.03, pp. 548-550
> + * Models 30h-3Fh Processors, Rev 3.06, pp. 610-612
> + */
> + base = 100000000; /* 100.0 MHz */
> + did = (def >> 6) & 0x7;
> + printf(" did %llu", did);
> + if (did >= 0x5) {
> + printf("(reserved)\n");
> + continue; /* reserved */
> + }
> + divisor = 1ULL << did;
> + fid = def & 0x3f;
> + multiplier = fid + 0x10;
> + printf(" divisor %llu base %llu fid %llu mul %llu",
> + divisor, base, fid, multiplier);
> + break;
> + case 0x17:
> + /*
> + * PPR for AMD Family 17h [...]:
> + * Models 01h,08h B2, Rev 3.03, pp. 33, 139-140
> + * Model 18h B1, Rev 3.16, pp. 36, 143-144
> + * Model 60h A1, Rev 3.06, pp. 33, 155-157
> + * Model 71h B0, Rev 3.06, pp. 28, 150-151
> + *
> + * OSRR for AMD Family 17h processors,
> + * Models 00h-2Fh, Rev 3.03, pp. 130-131
> + */
> + base = 200000000; /* 200.0 MHz */
> + divisor = did = (def >> 8) & 0x3f; /* XXX reserved vals? */
> + multiplier = fid = def & 0xff;
> + printf(" base %llu mul %llu div %llu",
> + base, multiplier, divisor);
> + break;
> + case 0x19:
> + /*
> + * PPR for AMD Family 19h
> + * Model 21h B0, Rev 3.05, pp. 33, 166-167
> + */
> + base = 200000000; /* 200.0 MHz */
> + divisor = did = (def >> 8) & 0x3f; /* XXX reserved vals? */
> + multiplier = fid = def & 0xff;
> + printf(" base %llu mul %llu div %llu",
> + base, multiplier, divisor);
> + break;
> + default:
> + return 0;
> + }
> + printf(" freq %llu Hz\n", base * multiplier / divisor);
> +}
> +/* DEBUG for-loop ends here. */
> +
> + return 0;
> +}
> +
> void
> tsc_identify(struct cpu_info *ci)
> {
> @@ -118,6 +365,8 @@ tsc_identify(struct cpu_info *ci)
> tsc_is_invariant = 1;
>
> tsc_frequency = tsc_freq_cpuid(ci);
> + if (tsc_frequency == 0)
> + tsc_frequency = tsc_freq_msr(ci);
> if (tsc_frequency > 0)
> delay_init(tsc_delay, 5000);
> }
> @@ -170,6 +419,8 @@ measure_tsc_freq(struct timecounter *tc)
> u_long s;
> int delay_usec, i, err1, err2, usec, success = 0;
>
> + printf("tsc: calibrating with %s: ", tc->tc_name);
> +
> /* warmup the timers */
> for (i = 0; i < 3; i++) {
> (void)tc->tc_get_timecount(tc);
> @@ -202,6 +453,8 @@ measure_tsc_freq(struct timecounter *tc)
> min_freq = MIN(min_freq, frequency);
> success++;
> }
> +
> + printf("%llu Hz\n", success > 1 ? min_freq : 0);
>
> return (success > 1 ? min_freq : 0);
> }
Hi,
Here's a dmesg from thinkpad e485:
Does these timers affect the booting of kernel? Once I select the kernel
to boot by pressing enter on "bsd>" line, the boot process takes about
18s to proceed from the "booting sr0a:/bsd".
Timo
OpenBSD 7.2 (GENERIC.MP) #20: Fri Sep 23 22:27:31 EEST 2022
t...@asteroid.bittivirhe.fi:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 16733204480 (15958MB)
avail mem = 16208670720 (15457MB)
random: good seed from bootblocks
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.1 @ 0x986eb000 (62 entries)
bios0: vendor LENOVO version "R0UET81W (1.61 )" date 03/17/2022
bios0: LENOVO 20KUCTO1WW
acpi0 at bios0: ACPI 5.0
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP SSDT SSDT CRAT CDIT SSDT TPM2 UEFI MSDM BATB HPET APIC
MCFG SBST WSMT VFCT IVRS FPDT SSDT SSDT SSDT BGRT UEFI SSDT
acpi0: wakeup devices GPP0(S3) GPP1(S3) GPP2(S3) GPP3(S3) GPP4(S3) GPP5(S3)
GPP6(S3) GP17(S3) XHC0(S3) XHC1(S3) GP18(S3) LID_(S3) SLPB(S3)
acpitimer0 at acpi0: 3579545 Hz, 32 bits
acpihpet0 at acpi0: 14318180 Hz
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: MSR C001_0064: en 1 base 200000000 mul 100 div 10 freq 2000000000 Hz
cpu0: MSR C001_0065: en 1 base 200000000 mul 102 div 12 freq 1700000000 Hz
cpu0: MSR C001_0066: en 1 base 200000000 mul 96 div 12 freq 1600000000 Hz
cpu0: MSR C001_0067: en 0
cpu0: MSR C001_0068: en 0
cpu0: MSR C001_0069: en 0
cpu0: MSR C001_006A: en 0
cpu0: MSR C001_006B: en 0
cpu0: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.30 MHz, 17-11-00
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
tsc: calibrating with acpihpet0: 1996264149 Hz
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
cpu0: apic clock running at 24MHz
cpu0: mwait min=64, max=64, C-substates=1.1, IBE
cpu1 at mainbus0: apid 1 (application processor)
cpu1: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.22 MHz, 17-11-00
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu1: smt 1, core 0, package 0
tsc: cpu0/cpu1: sync test failed
timecounter: active counter changed: tsc -> acpihpet0
cpu2 at mainbus0: apid 2 (application processor)
cpu2: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.22 MHz, 17-11-00
cpu2:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu2: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu2: smt 0, core 1, package 0
cpu3 at mainbus0: apid 3 (application processor)
cpu3: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00
cpu3:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu3: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu3: smt 1, core 1, package 0
cpu4 at mainbus0: apid 4 (application processor)
cpu4: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.22 MHz, 17-11-00
cpu4:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu4: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu4: smt 0, core 2, package 0
cpu5 at mainbus0: apid 5 (application processor)
cpu5: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00
cpu5:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu5: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu5: smt 1, core 2, package 0
cpu6 at mainbus0: apid 6 (application processor)
cpu6: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.22 MHz, 17-11-00
cpu6:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu6: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu6: smt 0, core 3, package 0
cpu7 at mainbus0: apid 7 (application processor)
cpu7: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00
cpu7:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu7: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu7: smt 1, core 3, package 0
ioapic0 at mainbus0: apid 32 pa 0xfec00000, version 21, 24 pins, can't remap
ioapic1 at mainbus0: apid 33 pa 0xfec01000, version 21, 32 pins, can't remap
acpimcfg0 at acpi0
acpimcfg0: addr 0xf8000000, bus 0-63
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 1 (GPP0)
acpiprt2 at acpi0: bus 2 (GPP1)
acpiprt3 at acpi0: bus 3 (GPP2)
acpiprt4 at acpi0: bus -1 (GPP3)
acpiprt5 at acpi0: bus -1 (GPP4)
acpiprt6 at acpi0: bus 4 (GPP5)
acpiprt7 at acpi0: bus -1 (GPP6)
acpiprt8 at acpi0: bus 5 (GP17)
acpiprt9 at acpi0: bus 6 (GP18)
acpiec0 at acpi0
acpibtn0 at acpi0: PWRB
acpipci0 at acpi0 PCI0: 0x00000010 0x00000011 0x00000000
acpicmos0 at acpi0
acpibat0 at acpi0: BAT0 model "01AV445" serial 2591 type LiP oem "LGC"
acpiac0 at acpi0: AC unit online
acpithinkpad0 at acpi0: version 2.0
"SMB0001" at acpi0 not configured
acpibtn1 at acpi0: LID_
acpibtn2 at acpi0: SLPB
"PNP0C14" at acpi0 not configured
"PNP0C14" at acpi0 not configured
"PNP0C14" at acpi0 not configured
tpm0 at acpi0 TPM_ 2.0 (TIS) addr 0xfed40000/0x5000, device 0x0000104a rev 0x4e
"USBC000" at acpi0 not configured
acpicpu0 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu1 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu2 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu3 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu4 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu5 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu6 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu7 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpipwrres0 at acpi0: P0ST, resource for SATA
acpipwrres1 at acpi0: P3ST, resource for SATA
acpivideo0 at acpi0: VGA_
acpivout0 at acpivideo0: LCD_
cpu0: 1996 MHz: speeds: 2000 1700 1600 MHz
pci0 at mainbus0 bus 0
ksmn0 at pci0 dev 0 function 0 "AMD 17h/1xh Root Complex" rev 0x00
"AMD 17h/1xh IOMMU" rev 0x00 at pci0 dev 0 function 2 not configured
pchb0 at pci0 dev 1 function 0 "AMD 17h PCIE" rev 0x00
ppb0 at pci0 dev 1 function 1 "AMD 17h/1xh PCIE" rev 0x00: msi
pci1 at ppb0 bus 1
nvme0 at pci1 dev 0 function 0 "Lenovo NVMe" rev 0x00: msix, NVMe 1.2
nvme0: LENSE20256GMSP34MEAT2TA, firmware 2.6.8341, serial 1227066205564
scsibus1 at nvme0: 2 targets, initiator 0
sd0 at scsibus1 targ 1 lun 0: <NVMe, LENSE20256GMSP34, 2.6.>
sd0: 244198MB, 512 bytes/sector, 500118192 sectors
ppb1 at pci0 dev 1 function 2 "AMD 17h/1xh PCIE" rev 0x00: msi
pci2 at ppb1 bus 2
re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x10: RTL8168GU/8111GU
(0x5080), msi, address e8:6a:64:33:83:cc
rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0
ppb2 at pci0 dev 1 function 3 "AMD 17h/1xh PCIE" rev 0x00: msi
pci3 at ppb2 bus 3
sdhc0 at pci3 dev 0 function 0 "O2 Micro 0Z8621 SD/MMC" rev 0x01: apic 33 int 8
sdhc0: SDHC 4.0, 50 MHz base clock
sdmmc0 at sdhc0: 4-bit, sd high-speed, mmc high-speed, ddr52, dma
ppb3 at pci0 dev 1 function 6 "AMD 17h/1xh PCIE" rev 0x00: msi
pci4 at ppb3 bus 4
iwm0 at pci4 dev 0 function 0 "Intel Dual Band Wireless-AC 8265" rev 0x78, msi
pchb1 at pci0 dev 8 function 0 "AMD 17h PCIE" rev 0x00
ppb4 at pci0 dev 8 function 1 "AMD 17h/1xh PCIE" rev 0x00
pci5 at ppb4 bus 5
amdgpu0 at pci5 dev 0 function 0 "ATI Radeon Vega" rev 0xc4
drm0 at amdgpu0
amdgpu0: msi
azalia0 at pci5 dev 0 function 1 "ATI Radeon Vega HD Audio" rev 0x00: msi
azalia0: no supported codecs
ccp0 at pci5 dev 0 function 2 "AMD 17h/1xh Crypto" rev 0x00
xhci0 at pci5 dev 0 function 3 "AMD 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10
usb0 at xhci0: USB revision 3.0
uhub0 at usb0 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
addr 1
xhci1 at pci5 dev 0 function 4 "AMD 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10
usb1 at xhci1: USB revision 3.0
uhub1 at usb1 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
addr 1
azalia1 at pci5 dev 0 function 6 "AMD 17h/1xh HD Audio" rev 0x00: apic 33 int 30
azalia1: codecs: Conexant/0x5111
audio0 at azalia1
ppb5 at pci0 dev 8 function 2 "AMD 17h/1xh PCIE" rev 0x00
pci6 at ppb5 bus 6
ahci0 at pci6 dev 0 function 0 "AMD FCH AHCI" rev 0x61: msi, AHCI 1.3.1
ahci0: port 0: 6.0Gb/s
scsibus2 at ahci0: 32 targets
sd1 at scsibus2 targ 0 lun 0: <ATA, Samsung SSD 850, EXM0> naa.50025388400c34c6
sd1: 488386MB, 512 bytes/sector, 1000215216 sectors, thin
piixpm0 at pci0 dev 20 function 0 "AMD FCH SMBus" rev 0x61: SMI
iic0 at piixpm0
admtemp0 at iic0 addr 0x18: Xeon
admtemp1 at iic0 addr 0x1a: Xeon
spdmem0 at iic0 addr 0x50: 8GB DDR4 SDRAM PC4-19200 SO-DIMM with thermal sensor
spdmem1 at iic0 addr 0x52: 8GB DDR4 SDRAM PC4-19200 SO-DIMM with thermal sensor
iic1 at piixpm0
pcib0 at pci0 dev 20 function 3 "AMD FCH LPC" rev 0x51
pchb2 at pci0 dev 24 function 0 "AMD 17h/1xh Data Fabric" rev 0x00
pchb3 at pci0 dev 24 function 1 "AMD 17h/1xh Data Fabric" rev 0x00
pchb4 at pci0 dev 24 function 2 "AMD 17h/1xh Data Fabric" rev 0x00
pchb5 at pci0 dev 24 function 3 "AMD 17h/1xh Data Fabric" rev 0x00
pchb6 at pci0 dev 24 function 4 "AMD 17h/1xh Data Fabric" rev 0x00
pchb7 at pci0 dev 24 function 5 "AMD 17h/1xh Data Fabric" rev 0x00
pchb8 at pci0 dev 24 function 6 "AMD 17h/1xh Data Fabric" rev 0x00
pchb9 at pci0 dev 24 function 7 "AMD 17h/1xh Data Fabric" rev 0x00
isa0 at pcib0
isadma0 at isa0
pckbc0 at isa0 port 0x60/5 irq 1 irq 12
pckbd0 at pckbc0 (kbd slot)
wskbd0 at pckbd0: console keyboard
pms0 at pckbc0 (aux slot)
wsmouse0 at pms0 mux 0
wsmouse1 at pms0 mux 0
pms0: Synaptics clickpad, firmware 8.16, 0x1e2b1 0x940300 0x373740 0xf016a3
0x12e800
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
vmm0 at mainbus0: SVM/RVI
efifb at mainbus0 not configured
vscsi0 at root
scsibus3 at vscsi0: 256 targets
softraid0 at root
scsibus4 at softraid0: 256 targets
sd2 at scsibus4 targ 1 lun 0: <OPENBSD, SR CRYPTO, 006>
sd2: 227678MB, 512 bytes/sector, 466284711 sectors
root on sd2a (88532b67c09ce3ee.a) swap on sd2b dump on sd2b
iwm0: hw rev 0x230, fw ver 36.ca7b901d.0, address 68:ec:c5:ad:9a:cb
amdgpu0: RAVEN 8 CU rev 0x01
amdgpu0: 1920x1080, 32bpp
wsdisplay0 at amdgpu0 mux 1: console (std, vt100 emulation), using wskbd0
wsdisplay0: screen 1-5 added (std, vt100 emulation)
