On Fri, Sep 23, 2022 at 10:40:19PM +0300, Timo Myyr?? wrote: > Scott Cheloha <scottchel...@gmail.com> [2022-09-23, 09:16 -0500]: > > > [...] > > > > Test results? Clues on reading the configuration space? > > > > [...] > > Hi, > > Here's a dmesg from thinkpad e485:
Thanks for testing. > Does these timers affect the booting of kernel? Once I select the kernel > to boot by pressing enter on "bsd>" line, the boot process takes about > 18s to proceed from the "booting sr0a:/bsd". The patch reads a couple MSRs and prints ~10 additional lines during boot from the primary CPU. The computed TSC frequency is not used by the kernel, only printed so I can check whether my code is correct. It should have zero impact on the length of the boot. It should not change any runtime behavior whatsoever. Your boot probably should not be taking that long, but I can't imagine how my patch would cause such a dramatic change. If you reverse the patch, what happens? > OpenBSD 7.2 (GENERIC.MP) #20: Fri Sep 23 22:27:31 EEST 2022 > t...@asteroid.bittivirhe.fi:/usr/src/sys/arch/amd64/compile/GENERIC.MP > [...] > cpu0 at mainbus0: apid 0 (boot processor) > cpu0: MSR C001_0064: en 1 base 200000000 mul 100 div 10 freq 2000000000 Hz > cpu0: MSR C001_0065: en 1 base 200000000 mul 102 div 12 freq 1700000000 Hz > cpu0: MSR C001_0066: en 1 base 200000000 mul 96 div 12 freq 1600000000 Hz > cpu0: MSR C001_0067: en 0 > cpu0: MSR C001_0068: en 0 > cpu0: MSR C001_0069: en 0 > cpu0: MSR C001_006A: en 0 > cpu0: MSR C001_006B: en 0 > cpu0: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.30 MHz, 17-11-00 > cpu0: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu0: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB > 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache > tsc: calibrating with acpihpet0: 1996264149 Hz Your family 17h CPU has a computed P0 frequency of 2000MHz. The calibrated TSC frequency is 1996264149 Hz. That seems right to me, thank you for testing.
