This is not helping. Please send Scott private replies regarding his diff.
Masato Asou <a...@soum.co.jp> wrote: > Hi, > > I have new AMD laptop. The dmesg is posted below: > > OpenBSD 7.2 (GENERIC.MP) #2: Mon Sep 26 09:09:17 JST 2022 > a...@hp-obsd.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP > real mem = 7844245504 (7480MB) > avail mem = 7589105664 (7237MB) > random: good seed from bootblocks > mpath0 at root > scsibus0 at mpath0: 256 targets > mainbus0 at root > bios0 at mainbus0: SMBIOS rev. 3.3 @ 0xbc55d000 (35 entries) > bios0: vendor AMI version "F.05" date 06/15/2022 > bios0: HP HP Laptop 14s-fq2xxx > acpi0 at bios0: ACPI 6.2Undefined scope: \\_SB_.PCI0.28 > > acpi0: sleep states S0 S4 S5 > acpi0: tables DSDT FACP MSDM SSDT IVRS SSDT FIDT MCFG HPET VFCT SSDT TPM2 > SSDT CRAT CDIT SSDT SSDT SSDT SSDT SSDT SSDT SSDT WSMT APIC SSDT SSDT SSDT > SSDT SSDT SSDT FPDT BGRT > acpi0: wakeup devices GPP1(S4) GP17(S4) GPP0(S4) > acpitimer0 at acpi0: 3579545 Hz, 32 bits > acpimcfg0 at acpi0 > acpimcfg0: addr 0xf0000000, bus 0-127 > acpihpet0 at acpi0: 14318180 Hz > acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat > cpu0 at mainbus0: apid 0 (boot processor) > cpu0: MSR C001_0064: en 1 base 200000000 mul 92 div 8 freq 2300000000 Hz > cpu0: MSR C001_0065: en 1 base 200000000 mul 90 div 10 freq 1800000000 Hz > cpu0: MSR C001_0066: en 1 base 200000000 mul 96 div 12 freq 1600000000 Hz > cpu0: MSR C001_0067: en 0 > cpu0: MSR C001_0068: en 0 > cpu0: MSR C001_0069: en 0 > cpu0: MSR C001_006A: en 0 > cpu0: MSR C001_006B: en 0 > cpu0: AMD Ryzen 5 5625U with Radeon Graphics, 2295.73 MHz, 19-50-00 > cpu0: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu0: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > tsc: calibrating with acpihpet0: 2295691309 Hz > cpu0: smt 0, core 0, package 0 > mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges > cpu0: apic clock running at 99MHz > cpu0: mwait min=64, max=64, C-substates=1.1, IBE > cpu1 at mainbus0: apid 1 (application processor) > cpu1: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu1: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu1: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu1: smt 1, core 0, package 0 > cpu2 at mainbus0: apid 2 (application processor) > cpu2: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu2: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu2: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu2: smt 0, core 1, package 0 > cpu3 at mainbus0: apid 3 (application processor) > cpu3: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu3: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu3: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu3: smt 1, core 1, package 0 > cpu4 at mainbus0: apid 4 (application processor) > cpu4: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu4: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu4: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu4: smt 0, core 2, package 0 > cpu5 at mainbus0: apid 5 (application processor) > cpu5: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu5: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu5: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu5: smt 1, core 2, package 0 > cpu6 at mainbus0: apid 6 (application processor) > cpu6: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu6: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu6: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu6: smt 0, core 3, package 0 > cpu7 at mainbus0: apid 7 (application processor) > cpu7: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu7: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu7: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu7: smt 1, core 3, package 0 > cpu8 at mainbus0: apid 8 (application processor) > cpu8: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu8: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu8: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu8: smt 0, core 4, package 0 > cpu9 at mainbus0: apid 9 (application processor) > cpu9: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu9: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu9: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu9: smt 1, core 4, package 0 > cpu10 at mainbus0: apid 10 (application processor) > cpu10: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu10: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu10: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu10: smt 0, core 5, package 0 > cpu11 at mainbus0: apid 11 (application processor) > cpu11: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu11: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu11: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu11: smt 1, core 5, package 0 > ioapic0 at mainbus0: apid 33 pa 0xfec00000, version 21, 24 pins, can't remap > ioapic1 at mainbus0: apid 34 pa 0xfec01000, version 21, 32 pins, can't remap > acpiprt0 at acpi0: bus 0 (PCI0) > acpiprt1 at acpi0: bus -1 (GPP1) > acpiprt2 at acpi0: bus 1 (GPP4) > acpiprt3 at acpi0: bus -1 (GPP5) > acpiprt4 at acpi0: bus 3 (GP17) > acpiprt5 at acpi0: bus -1 (GP18) > acpiprt6 at acpi0: bus -1 (GP19) > acpiprt7 at acpi0: bus 2 (GPP6) > acpiprt8 at acpi0: bus -1 (GPP0) > acpiprt9 at acpi0: bus -1 (BR32) > acpiprt10 at acpi0: bus -1 (BR33) > acpiec0 at acpi0 > acpipci0 at acpi0 PCI0: 0x00000010 0x00000011 0x00000000 > acpicmos0 at acpi0 > "HPIC0003" at acpi0 not configured > acpibtn0 at acpi0: PWRB > "ACPI0010" at acpi0 not configured > acpicpu0 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu1 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu2 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu3 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu4 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu5 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu6 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu7 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu8 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu9 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu10 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu11 at acpi0: C3(0@350 io@0x415), C2(0@18 io@0x414), C1(0@1 mwait), PSS > acpicpu12 at acpi0: no cpu matching ACPI ID 13 > acpicpu13 at acpi0: no cpu matching ACPI ID 14 > acpicpu14 at acpi0: no cpu matching ACPI ID 15 > acpicpu15 at acpi0: no cpu matching ACPI ID 16 > amdgpio0 at acpi0 GPIO uid 0 addr 0xfed81500/0x400 irq 7, 184 pins > dwiic0 at acpi0 I2CA addr 0xfedc2000/0x1000 irq 10 > iic0 at dwiic0 > dwiic1 at acpi0 I2CD addr 0xfedc5000/0x1000 irq 6 > iic1 at dwiic1 > ihidev0 at iic1 addr 0x2c gpio 9, vendor 0x6cb product 0xcd50, SYNA32C2 > ihidev0: 31 report ids > imt0 at ihidev0: clickpad, 5 contacts > wsmouse0 at imt0 mux 0 > ims0 at ihidev0 reportid 2: 2 buttons > wsmouse1 at ims0 mux 0 > hid at ihidev0 reportid 6 not configured > hid at ihidev0 reportid 7 not configured > hid at ihidev0 reportid 9 not configured > hid at ihidev0 reportid 10 not configured > hid at ihidev0 reportid 11 not configured > hid at ihidev0 reportid 12 not configured > hid at ihidev0 reportid 13 not configured > hid at ihidev0 reportid 14 not configured > hid at ihidev0 reportid 15 not configured > hid at ihidev0 reportid 29 not configured > hid at ihidev0 reportid 31 not configured > tpm0 at acpi0 TPM_: unsupported TPM2 start method 2 > "ACPI000E" at acpi0 not configured > "PNP0C14" at acpi0 not configured > acpibat0 at acpi0: BAT0 model "Primary" serial SerialNumber type LION oem "HP" > acpiac0 at acpi0: AC unit online > acpibtn1 at acpi0: LID_ > "AMDI0051" at acpi0 not configured > "AMDI0005" at acpi0 not configured > "PNP0C14" at acpi0 not configured > acpipwrres0 at acpi0: PRBT > acpipwrres1 at acpi0: P0U0, resource for XHC0 > acpipwrres2 at acpi0: P3U0, resource for XHC0 > acpipwrres3 at acpi0: P0U1, resource for XHC1 > acpipwrres4 at acpi0: P3U1, resource for XHC1 > acpipwrres5 at acpi0: P0SA, resource for SATA > acpipwrres6 at acpi0: P0SA, resource for SAT1 > acpipwrres7 at acpi0: P0NV, resource for NVME > acpipwrres8 at acpi0: PRWL > acpipwrres9 at acpi0: PRWB > acpitz0 at acpi0: critical temperature is 255 degC > acpivideo0 at acpi0: VGA_ > acpivout0 at acpivideo0: LCD_ > acpivideo1 at acpi0: VGA_ > cpu0: 2295 MHz: speeds: 2300 1800 1600 MHz > pci0 at mainbus0 bus 0 > ksmn0 at pci0 dev 0 function 0 "AMD 17h/6xh Root Complex" rev 0x00 > "AMD 17h/6xh IOMMU" rev 0x00 at pci0 dev 0 function 2 not configured > pchb0 at pci0 dev 1 function 0 "AMD 17h/6xh Host" rev 0x00 > pchb1 at pci0 dev 2 function 0 "AMD 17h/6xh Host" rev 0x00 > ppb0 at pci0 dev 2 function 2 "AMD 17h/6xh PCIE" rev 0x00: msi > pci1 at ppb0 bus 1 > vendor "Realtek", unknown product 0xb852 (class network subclass > miscellaneous, rev 0x00) at pci1 dev 0 function 0 not configured > ppb1 at pci0 dev 2 function 4 "AMD 17h/6xh PCIE" rev 0x00: msi > pci2 at ppb1 bus 2 > nvme0 at pci2 dev 0 function 0 "Kioxia BG4" rev 0x00: msix, NVMe 1.3 > nvme0: KBG40ZNV256G KIOXIA, firmware HP01AE00, serial 528PGJ57QX74 > scsibus1 at nvme0: 2 targets, initiator 0 > sd0 at scsibus1 targ 1 lun 0: <NVMe, KBG40ZNV256G KIO, HP01> > sd0: 244198MB, 512 bytes/sector, 500118192 sectors > pchb2 at pci0 dev 8 function 0 "AMD 17h/6xh Host" rev 0x00 > ppb2 at pci0 dev 8 function 1 "AMD 17h/6xh PCIE" rev 0x00 > pci3 at ppb2 bus 3 > amdgpu0 at pci3 dev 0 function 0 "ATI Barcelo" rev 0xc2 > drm0 at amdgpu0 > amdgpu0: msi > azalia0 at pci3 dev 0 function 1 "ATI Renoir HD Audio" rev 0x00: msi > azalia0: no supported codecs > ccp0 at pci3 dev 0 function 2 "AMD 17h/1xh Crypto" rev 0x00 > xhci0 at pci3 dev 0 function 3 "AMD 17h/6xh xHCI" rev 0x00: msi, xHCI 1.10 > usb0 at xhci0: USB revision 3.0 > uhub0 at usb0 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00 > addr 1 > xhci1 at pci3 dev 0 function 4 "AMD 17h/6xh xHCI" rev 0x00: msi, xHCI 1.10 > usb1 at xhci1: USB revision 3.0 > uhub1 at usb1 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00 > addr 1 > "AMD 17h/1xh I2S Audio" rev 0x01 at pci3 dev 0 function 5 not configured > azalia1 at pci3 dev 0 function 6 "AMD 17h/1xh HD Audio" rev 0x00: apic 34 int > 12 > azalia1: codecs: Realtek ALC236 > audio0 at azalia1 > piixpm0 at pci0 dev 20 function 0 "AMD FCH SMBus" rev 0x51: polling > iic2 at piixpm0 > iic3 at piixpm0 > pcib0 at pci0 dev 20 function 3 "AMD FCH LPC" rev 0x51 > pchb3 at pci0 dev 24 function 0 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb4 at pci0 dev 24 function 1 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb5 at pci0 dev 24 function 2 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb6 at pci0 dev 24 function 3 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb7 at pci0 dev 24 function 4 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb8 at pci0 dev 24 function 5 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb9 at pci0 dev 24 function 6 "AMD 19h/5xh Data Fabric" rev 0x00 > pchb10 at pci0 dev 24 function 7 "AMD 19h/5xh Data Fabric" rev 0x00 > isa0 at pcib0 > isadma0 at isa0 > pckbc0 at isa0 port 0x60/5 irq 1 irq 12 > pckbd0 at pckbc0 (kbd slot) > wskbd0 at pckbd0: console keyboard > pms0 at pckbc0 (aux slot) > wsmouse2 at pms0 mux 0 > pms0: Synaptics clickpad, firmware 10.16, 0x1e2a1 0x840300 0x365040 0xf00923 > 0x12e800 > pcppi0 at isa0 port 0x61 > spkr0 at pcppi0 > vmm0 at mainbus0: SVM/RVI > efifb at mainbus0 not configured > uvideo0 at uhub0 port 3 configuration 1 interface 0 "DMWCR0AG4GE2IE HP > TrueVision HD Camera" rev 2.01/0.03 addr 2 > video0 at uvideo0 > ugen0 at uhub0 port 3 configuration 1 "DMWCR0AG4GE2IE HP TrueVision HD > Camera" rev 2.01/0.03 addr 2 > ugen1 at uhub0 port 4 "Realtek Bluetooth Radio" rev 1.00/0.00 addr 3 > umass0 at uhub0 port 6 configuration 1 interface 0 "JMicron External" rev > 3.20/2.04 addr 4 > umass0: using SCSI over Bulk-Only > scsibus2 at umass0: 2 targets, initiator 0 > sd1 at scsibus2 targ 1 lun 0: <JMicron, Tech, 0204> > serial.152d0562D56419883893 > sd1: 953869MB, 512 bytes/sector, 1953525168 sectors > axe0 at uhub1 port 2 configuration 1 interface 0 "ASIX Electronics AX88772" > rev 2.00/0.01 addr 2 > axe0: AX88772, address 00:90:cc:e8:15:5b > ukphy0 at axe0 phy 16: Generic IEEE 802.3u media interface, rev. 1: OUI > 0x000ec6, model 0x0001 > ugen2 at uhub1 port 4 "ELAN ELAN:ARM-M4" rev 2.00/2.81 addr 3 > vscsi0 at root > scsibus3 at vscsi0: 256 targets > softraid0 at root > scsibus4 at softraid0: 256 targets > root on sd1a (492957bfc38a2933.a) swap on sd1b dump on sd1b > amdgpu0: GREEN_SARDINE 7 CU rev 0x00 > amdgpu0: 1920x1080, 32bpp > wsdisplay0 at amdgpu0 mux 1: console (std, vt100 emulation), using wskbd0 > wsdisplay0: screen 1-5 added (std, vt100 emulation) > > -- > ASOU Masato > > From: Scott Cheloha <scottchel...@gmail.com> > Date: Fri, 23 Sep 2022 09:16:25 -0500 > > > Hi, > > > > TL;DR: > > > > I want to compute the TSC frequency on AMD CPUs using the methods laid > > out in the AMD manuals instead of calibrating the TSC by hand. > > > > If you have an AMD CPU with an invariant TSC, please apply this patch, > > recompile/boot the resulting kernel, and send me the resulting dmesg. > > > > Family 10h-16h CPUs are especially interesting. If you've got one, > > don't be shy! > > > > Long explanation: > > > > On AMD CPUs we calibrate the TSC with a separate timer. This is slow > > and introduces error. I also worry about a future where legacy timers > > are absent or heavily gated (read: useless). > > > > This patch adds most of the code needed to compute the TSC frequency > > on AMD family 10h+ CPUs. CPUs prior to family 10h did not support an > > invariant TSC so they are irrelevant. > > > > I have riddled the code with printf(9) calls so I can work out what's > > wrong by hand if a test result makes no sense. > > > > The only missing piece is code to read the configuration space on > > family 10h-16h CPUs to determine how many boosted P-states we need to > > skip to get to the MSR describing the software P0 state. I would > > really appreciate it if someone could explain how to do this at this > > very early point in boot. jsg@ pointed me to pci_conf_read(9), but > > I'm a little confused about how I get the needed pci* inputs at this > > point in boot. > > > > -- > > > > Test results? Clues on reading the configuration space? > > > > -Scott > > > > Index: tsc.c > > =================================================================== > > RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v > > retrieving revision 1.29 > > diff -u -p -r1.29 tsc.c > > --- tsc.c 22 Sep 2022 04:57:08 -0000 1.29 > > +++ tsc.c 23 Sep 2022 14:04:22 -0000 > > @@ -100,6 +100,253 @@ tsc_freq_cpuid(struct cpu_info *ci) > > return (0); > > } > > > > +uint64_t > > +tsc_freq_msr(struct cpu_info *ci) > > +{ > > + uint64_t base, def, did, did_lsd, did_msd, divisor, fid, multiplier; > > + uint32_t msr, off = 0; > > + > > + if (strcmp(cpu_vendor, "AuthenticAMD") != 0) > > + return 0; > > + > > + /* > > + * All family 10h+ CPUs have MSR_HWCR and the TscFreqSel bit. > > + * If TscFreqSel is not set the TSC does not advance at the P0 > > + * frequency, in which case something is wrong and we need to > > + * calibrate by hand. > > + */ > > +#define HWCR_TSCFREQSEL (1 << 24) > > + if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL)) /* XXX specialreg.h */ > > + return 0; > > +#undef HWCR_TSCFREQSEL > > + > > + /* > > + * For families 10h, 12h, 14h, 15h, and 16h, we need to skip past > > + * the boosted P-states (Pb0, Pb1, etc.) to find the MSR describing > > + * P0, i.e. the highest performance unboosted P-state. The number > > + * of boosted states is kept in the "Core Performance Boost Control" > > + * configuration space register. > > + */ > > +#ifdef __not_yet__ > > + uint32_t reg; > > + switch (ci->ci_family) { > > + case 0x10: > > + /* XXX How do I read config space at this point in boot? */ > > + reg = read_config_space(F4x15C); > > + off = (reg >> 2) & 0x1; > > + break; > > + case 0x12: > > + case 0x14: > > + case 0x15: > > + case 0x16: > > + /* XXX How do I read config space at this point in boot? */ > > + reg = read_config_space(D18F4x15C); > > + off = (reg >> 2) & 0x7; > > + break; > > + default: > > + break; > > + } > > +#endif > > + > > +/* DEBUG Let's look at all the MSRs to check my math. */ > > +for (; off < 8; off++) { > > + > > + /* > > + * In family 10h+, core P-state voltage/frequency definitions > > + * are kept in MSRs C001_006[4:B] (eight registers in total). > > + * All MSRs in the range are readable, but if the EN bit isn't > > + * set the register doesn't define a valid P-state. > > + */ > > + msr = 0xc0010064 + off; /* XXX specialreg.h */ > > + def = rdmsr(msr); > > + printf("%s: MSR %04X_%04X: en %d", > > + ci->ci_dev->dv_xname, msr >> 16, msr & 0xffff, > > + !!ISSET(def, 1ULL << 63)); > > + if (!ISSET(def, 1ULL << 63)) { /* XXX specialreg.h */ > > + printf("\n"); > > + continue; > > + } > > + switch (ci->ci_family) { > > + case 0x10: > > + /* AMD Family 10h Processor BKDG, Rev 3.62, p. 429 */ > > + base = 100000000; /* 100.0 MHz */ > > + did = (def >> 6) & 0x7; > > + divisor = 1ULL << did; > > + fid = def & 0x1f; > > + multiplier = fid + 0x10; > > + printf(" base %llu did %llu div %llu fid %llu mul %llu", > > + base, did, divisor, fid, multiplier); > > + break; > > + case 0x11: > > + /* AMD Family 11h Processor BKDG, Rev 3.62, p. 236 */ > > + base = 100000000; /* 100.0 MHz */ > > + did = (def >> 6) & 0x7; > > + divisor = 1ULL << did; > > + fid = def & 0x1f; > > + multiplier = fid + 0x8; > > + printf(" base %llu did %llu div %llu fid %llu mul %llu", > > + base, did, divisor, fid, multiplier); > > + break; > > + case 0x12: > > + /* AMD Family 12h Processor BKDG, Rev 3.02, pp. 468-469 */ > > + base = 100000000; /* 100.0 MHz */ > > + fid = (def >> 4) & 0xf; > > + multiplier = fid + 0x10; > > + > > + /* > > + * A CpuDid of 1 maps to a divisor of 1.5. To simulate > > + * this with integer math we use a divisor of 3 and double > > + * the multiplier, as (X * 2 / 3) equals (X / 1.5). All > > + * other CpuDid values map to to whole number divisors > > + * or are reserved. > > + */ > > + did = def & 0xf; > > + printf(" did %llu", did); > > + if (did >= 8) { > > + printf("(reserved)\n"); > > + continue; /* reserved */ > > + } > > + if (did == 1) > > + multiplier *= 2; > > + uint64_t did_divisor[] = { 1, 3, 2, 3, 4, 6, 8, 12, 16 }; > > + divisor = did_divisor[did]; > > + printf(" div %llu base %llu fid %llu mul %llu", > > + divisor, base, fid, multiplier); > > + break; > > + case 0x14: > > + /* > > + * BKDG for AMD Family 14h Models 00h-0Fh Processors, > > + * Rev 3.13, pp. 428-429 > > + * > > + * Family 14h doesn't have CpuFid or CpuDid. Instead, > > + * the CpuCOF divisor is derived from two new fields: > > + * CpuDidMsd, the integral base, and CpuDidLsd, the > > + * fractional multiplier. The formula for the divisor > > + * varies with the magnitude of CpuDidMsd: > > + * > > + * CpuDidMsd <= 14: CpuDidMsd + 1 + (CpuDidLsd * 0.25) > > + * CpuDidMsd >= 15: CpuDidMsd + 1 + ((CpuDidLsd & 0x10) * 0.25) > > + * > > + * CpuCOF is just (base / divisor), however we need to > > + * multiply both sides by 100 to simulate fractional > > + * division with integer math, e.g. (X * 100 / 125) is > > + * equivalent to (X / 1.25). > > + */ > > +#if __not_yet__ > > + /* XXX How do I read config space at this point in boot? */ > > + reg = read_config_space(D18F3xD4); > > + base = 100000000 * ((reg & 0x3f) + 0x10); > > +#else > > + base = 100000000; /* XXX guess 100.0 MHz for now... */ > > +#endif > > + multiplier = 100; > > + did_msd = (def >> 4) & 0x19; > > + printf(" msd %llu", did_msd); > > + if (did_msd >= 27) { > > + printf("(reserved)\n"); > > + continue; /* XXX might be reserved? */ > > + } > > + did_lsd = def & 0xf; > > + printf(" lsd %llu", did_lsd); > > + if (did_lsd >= 4) { > > + printf("(reserved)\n"); > > + continue; /* reserved */ > > + } > > + if (did_msd >= 15) > > + did_lsd &= 0x10; > > + divisor = (did_msd + 1) * 100 + (did_lsd * 25); > > + printf(" div %llu base %llu mul %llu", > > + divisor, base, multiplier); > > + break; > > + case 0x15: > > + /* > > + * BKDG for AMD Family 15h [...]: > > + * Models 00h-OFh Processors, Rev 3.14, pp. 569-571 > > + * Models 10h-1Fh Processors, Rev 3.12, pp. 580-581 > > + * Models 30h-3Fh Processors, Rev 3.06, pp. 634-636 > > + * Models 60h-6Fh Processors, Rev 3.05, pp. 691-693 > > + * Models 70h-7Fh Processors, Rev 3.09, pp. 655-656 > > + */ > > + base = 100000000; /* 100.0 Mhz */ > > + did = (def >> 6) & 0x7; > > + printf(" base %llu did %llu", base, did); > > + if (did >= 0x5) { > > + printf("(reserved)\n"); > > + continue; /* reserved */ > > + } > > + divisor = 1ULL << did; > > + > > + /* > > + * BKDG for AMD Family 15h Models 00h-0Fh, Rev 3.14, p. 571 > > + * says that "CpuFid must be less than or equal to 2Fh." > > + * No other BKDG for family 15h limits the range of CpuFid. > > + */ > > + fid = def & 0x3f; > > + printf(" fid %llu", fid); > > + if (ci->ci_model <= 0x0f && fid >= 0x30) { > > + printf("(reserved)\n"); > > + continue; /* reserved */ > > + } > > + multiplier = fid + 0x10; > > + printf(" mul %llu div %llu", multiplier, divisor); > > + break; > > + case 0x16: > > + /* > > + * BKDG for AMD Family 16h [...]: > > + * Models 00h-0Fh Processors, Rev 3.03, pp. 548-550 > > + * Models 30h-3Fh Processors, Rev 3.06, pp. 610-612 > > + */ > > + base = 100000000; /* 100.0 MHz */ > > + did = (def >> 6) & 0x7; > > + printf(" did %llu", did); > > + if (did >= 0x5) { > > + printf("(reserved)\n"); > > + continue; /* reserved */ > > + } > > + divisor = 1ULL << did; > > + fid = def & 0x3f; > > + multiplier = fid + 0x10; > > + printf(" divisor %llu base %llu fid %llu mul %llu", > > + divisor, base, fid, multiplier); > > + break; > > + case 0x17: > > + /* > > + * PPR for AMD Family 17h [...]: > > + * Models 01h,08h B2, Rev 3.03, pp. 33, 139-140 > > + * Model 18h B1, Rev 3.16, pp. 36, 143-144 > > + * Model 60h A1, Rev 3.06, pp. 33, 155-157 > > + * Model 71h B0, Rev 3.06, pp. 28, 150-151 > > + * > > + * OSRR for AMD Family 17h processors, > > + * Models 00h-2Fh, Rev 3.03, pp. 130-131 > > + */ > > + base = 200000000; /* 200.0 MHz */ > > + divisor = did = (def >> 8) & 0x3f; /* XXX reserved vals? */ > > + multiplier = fid = def & 0xff; > > + printf(" base %llu mul %llu div %llu", > > + base, multiplier, divisor); > > + break; > > + case 0x19: > > + /* > > + * PPR for AMD Family 19h > > + * Model 21h B0, Rev 3.05, pp. 33, 166-167 > > + */ > > + base = 200000000; /* 200.0 MHz */ > > + divisor = did = (def >> 8) & 0x3f; /* XXX reserved vals? */ > > + multiplier = fid = def & 0xff; > > + printf(" base %llu mul %llu div %llu", > > + base, multiplier, divisor); > > + break; > > + default: > > + return 0; > > + } > > + printf(" freq %llu Hz\n", base * multiplier / divisor); > > +} > > +/* DEBUG for-loop ends here. */ > > + > > + return 0; > > +} > > + > > void > > tsc_identify(struct cpu_info *ci) > > { > > @@ -118,6 +365,8 @@ tsc_identify(struct cpu_info *ci) > > tsc_is_invariant = 1; > > > > tsc_frequency = tsc_freq_cpuid(ci); > > + if (tsc_frequency == 0) > > + tsc_frequency = tsc_freq_msr(ci); > > if (tsc_frequency > 0) > > delay_init(tsc_delay, 5000); > > } > > @@ -170,6 +419,8 @@ measure_tsc_freq(struct timecounter *tc) > > u_long s; > > int delay_usec, i, err1, err2, usec, success = 0; > > > > + printf("tsc: calibrating with %s: ", tc->tc_name); > > + > > /* warmup the timers */ > > for (i = 0; i < 3; i++) { > > (void)tc->tc_get_timecount(tc); > > @@ -202,6 +453,8 @@ measure_tsc_freq(struct timecounter *tc) > > min_freq = MIN(min_freq, frequency); > > success++; > > } > > + > > + printf("%llu Hz\n", success > 1 ? min_freq : 0); > > > > return (success > 1 ? min_freq : 0); > > } > > >