http://defect.opensolaris.org/bz/show_bug.cgi?id=4015
Eric Saxe <eric.saxe at sun.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|FIXINPROGRESS |CLOSED
Resolution| |FIXED
--- Comment #8 from Eric Saxe <eric.saxe at sun.com> 2008-10-23 14:12:30 ---
I have a fix:
Before:
> *cpu_list::print cpu_t cpu_pg |::print cpu_pg_t cmt_pgs |::walk group
> |::print pghw_t pghw_hw
pghw_hw = 8 (PGHW_POW_IDLE)
pghw_hw = 7 (PGHW_POW_ACTIVE)
pghw_hw = 5 (PGHW_CHIP)
pghw_hw = 2 (PGHW_CACHE)
pghw_hw = 1 (PGHW_IPIPE)
Fix in place:
> *cpu_list::print cpu_t cpu_pg |::print cpu_pg_t cmt_pgs |::walk group
> |::print pghw_t pghw_hw
pghw_hw = 5 (PGHW_CHIP)
pghw_hw = 7 (PGHW_POW_ACTIVE)
pghw_hw = 2 (PGHW_CACHE)
pghw_hw = 8 (PGHW_POW_IDLE)
pghw_hw = 1 (PGHW_IPIPE)
I verified that the lineage is the same for the other CPUs in the system.
As an artifact of the fix, the power domain PG and the socket PG (chip)'s order
has flipped, which will undermine the coalescing policy. This is still legal,
since it's the same set of CPUs for both, and there's nothing in place to
prefer one over the other. This needs to be fixed so that the level/grouping
implementing the non-preferred policy (load balancing or coalescing) is either
demoted in the lineages or removed. This will be addressed as a separate fix.
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