http://defect.opensolaris.org/bz/show_bug.cgi?id=5837
Aubrey.Li <aubrey.li at intel.com> changed:
What |Removed |Added
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CC| |aubrey.li at intel.com
--- Comment #2 from Aubrey.Li <aubrey.li at intel.com> 2008-12-18 00:04:10 ---
If I guess correctly, _CST of other cpus(not including cpu0) need to be
exported by evaluating PDC with bit3 setting on your system. Currently, this
bit is only available when speedstep is supported. If so, this bug should
remain in the current pad-gate tip 8099.
I believe throttling has the same problem, here is a patch against it.
I'll commit it if the problem is gone.
=================
diff -r 219611fccc4a usr/src/uts/i86pc/os/cpupm/cpupm_intel.c
--- a/usr/src/uts/i86pc/os/cpupm/cpupm_intel.c Wed Dec 17 20:51:33 2008 -0500
+++ b/usr/src/uts/i86pc/os/cpupm/cpupm_intel.c Thu Feb 21 08:16:43 2008 +0800
@@ -84,7 +84,7 @@
*/
mach_state->ms_tstate.cma_ops = &cpupm_throttle_ops;
cpupm_intel_pdccap |= CPUPM_INTEL_PDC_TS_MSR |
- CPUPM_INTEL_PDC_TSD;
+ CPU_INTEL_PDC_MP | CPUPM_INTEL_PDC_TSD;
/*
* If we support deep cstates on this processor, then set the
@@ -93,7 +93,8 @@
*/
mach_state->ms_cstate.cma_ops = &cpu_idle_ops;
cpupm_intel_pdccap |= CPUPM_INTEL_PDC_C1_HALT |
- CPUPM_INTEL_PDC_C2C3_MP | CPUPM_INTEL_PDC_C1_FFH;
+ CPUPM_INTEL_PDC_MP | CPUPM_INTEL_PDC_C2C3_MP |
+ CPUPM_INTEL_PDC_C1_FFH;
/*
* _PDC support is optional and the driver should
================
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