http://defect.opensolaris.org/bz/show_bug.cgi?id=3128
Summary: Cleanup interrupt selection for HPET
Classification: Development
Product: power-mgmt
Version: unspecified
Platform: Other
OS/Version: Solaris
Status: NEW
Severity: critical
Priority: P2
Component: c-state
AssignedTo: bill.holler at sun.com
ReportedBy: bill.holler at sun.com
CC: tesla-dev at opensolaris.org
Estimated Hours: 0.0
The interrupt used by the HPET is currently hard coded to 11 because an old ICH
(7?) document listed interrupt 11 as dedicated to the HPET.
The HPET interrupt is edge triggered and unshared for performance.
Deep C-states should not use HPET timers 0 and 1. These are intended
for legacy timer replacement. The HPET specification frightens us
with talk of the PIT and RT timers going away some day. HPET timese 0 and 1
are to replace these.
Several HPET's on test systems have timers 2 and 3 with these Interrupt
Route Capabilities: 2 = f00800, and 3 = f01000.
f00800 indicates timer 2 can be routed to I/O APIC interrupt 11.
Solaris should use the Interrupt Capabilities Registers of timer 2 and up
to determine which I/O APIC interrupt to use.
Solaris should use level triggered interrupts? Edge triggered, unshared
interrupts where used because this may be a heavily used interrupt on idle
systems. Testing indicates writing to the HPET's General Interrupt Status
Register T#_INT_STS bit to clear the interrupt may not be as expensive as
expected.
The hpet_isr might just run without checking the timer's T#_INT_STS bit?
We might not have to clear this bit.
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