It took a little longer than expected, but Solaris support for Intel
Enhanced Speedstep just integrated into Nevada. It's implemented as a
CPU driver that is managed by the Solaris Power Management Framework.
A couple of requirements need to be met in order for the driver to
support Enhanced Speedstep:
1 - The processor's TSC must be P-State TSC invariant. Seems that this
translates to
Intel processor families 0xF (models >= 0x3) and 0x6 (models >=
0xE). I know that
this includes (at least) Pentium 4, Xeon, Core and Core Duo.
2 - BIOS support. Frequently, there is a BIOS setting that enables/disables
Enhanced Speedstep. It needs to be enabled *and* when it is enabled
the BIOS
needs to export sound ACPI data (i.e., good _PSS tables).
As I think I mentioned in an earlier thread, the PM framework
(currently, at least) places some limitations on the rate at which CPUs
can switch P-States. Specifically, the framework scans at 15 second
intervals to see if a device should be transitioned to a lower power
level (raising power levels can happen at any interval). Obviously, this
is going to be unacceptable long-term. One of the things we'll have to
figure out as part of tesla is whether or not CPU power management can
continue to be implemented in this way (with modifications to the PM
framework to allow for more frequent scans of CPU devices). If not, then
we'll have to figure out how CPU power management fits into the existing
PM story (in particular suspend/resume).
In any case, we have a start.
Mark
