Bill Holler wrote:
> Are _CSD/c-state domains "flat", or can these be in a tree?
> For example if there is a 4-core chip with two shared caches?
>
> I am having a hard time envisioning how the PAD will place
> threads across both _PSD and _CSD defined domains.
> Would the PAD prefer high p-state domains, and then
> lower p-state domains, and then lower c-state domains last?
>
>
We can implement a hierarchical coalescence thread placement policy, to
consolidate load across several levels.
For example, consolidating load onto a single socket, and then within
that socket, consolidating load onto the CPU's sharing a core, or a
cache. I'm trying to figure out what the "grouping" strategies should
be, such that when we implement the above policy, it saves the most power.
It sounds like since P-states capture both frequency and voltage,
there's good incentive to try and quiesce all CPUs sharing a P-state
domain, since we can then get all CPUs into the lowest P-state, thereby
allowing both the voltage and frequency to drop.
For _CSD groups, one consideration for the dispatcher might be the order
in which the available idle CPUs on the system are utilized as
utilization ramps up. If we have to schedule a thread somewhere to run,
we would want to prefer to use CPUs in a _CSD that are in a relatively
shallow c-state, and avoid ones (if possible) that are sleeping
deeply...and I think those sorts of considerations should be made across
the groups of CPUs in _CSDs, and not on a CPU by CPU basis.
For each CPU, we could create two groupings that capture the above:
- The CPUs sharing an "active" performance/power state.
- The CPUs sharing an "idle/sleeping" state.
...and the dispatcher could implement both bits of scheduling policy
across these two classes of groups...
-Eric
