Andrei Dorofeev wrote: > My Intel contact told me this. I couldn't find this info anywhere in > the docs.
Thanks anyway, let me have a try. -Aubrey > > On Thu, Feb 21, 2008 at 10:40 PM, Li, Aubrey > <aubrey.li at intel.com> wrote: >> Andrei Dorofeev wrote: >> >> > Both TSC and LAPIC timer keep ticking in C2 so it's pretty safe >> to use > instead of C1 (HLT/MWAIT). The latency is only ~4 times >> > longer than HLT. >> >> Thanks for the info. >> But, where is documented? >> >> -Aubrey >> >> >> >> > >> > On Thu, Feb 21, 2008 at 10:06 PM, Li, Aubrey >> > <aubrey.li at intel.com> wrote: >> >> I was told TSC will stop in deeper c-state. But I tried the >> >> CPU_ACPI_C2 code path I wrote, the system works fine in C2. So, >> >> this is really a good question. I'll try to see if I can find >> some >> docs about this issue.
