Andrei Dorofeev wrote: > I was talking about processor C2 state, which can be entered directly > with monitor/mwait.
We should cover the platform which don't support monitor/mwait, but it's ACPI compliant and supports deep c-state. > > Do you have more information about which OEMs do what you > describe here (mapping processor C3+ state to ACPI C2)? No name info at this moment. Thanks, -Aubrey > > On Thu, Feb 21, 2008 at 11:31 PM, Li, Aubrey > <aubrey.li at intel.com> wrote: >> Andrei Dorofeev wrote: >> >> > Both TSC and LAPIC timer keep ticking in C2 so it's pretty safe >> to use > instead of C1 (HLT/MWAIT). The latency is only ~4 times >> > longer than HLT. >> >> Hmm..., the caveat is that at more than one OEM maps the C3/C4/C5 >> states to ACPI C2, so we can't guarantee TSC works in ACPI C2. >> >> -Aubrey
