Hi All,
Can anyone give me the low-down on logic standards for clock distribution in digital systems? It seems that ECL, PECL and LVDS are the most widely used. After a quick glance at the specs for the above mentioned standards I noted the following differences between ECL/PECL and LVDS: Although ECL/PECL is faster and can be distributed along longer lengths of cable it requires more power and produce more noise. Also the input sensitivity of LVDS is twice that of ECL/PECL. So logically, I can conclude that one should use ECL/PECL for clock distribution along long lengths of cable and LVDS for shorter ones. However, there are a number of questions that spring to mind. Even when distributing a low frequency digital signal, for example a 10MHz frequency reference, one is in reality faced with a high-speed digital problem. One explicitly wants the signal to have fast edges so that it is effectively immunized against amplitude/temperature/power supply variations. The faster the edge (or rise time) the lower the delta t (or jitter) in response to the mentioned variations. However, faster edges give rise to various problems such as crosstalk, EMI and reflections&ringing. I guess that another approach would be to differentially transmit the clock in sinusoidal format where after it is heavily filtered and squared at the receiving end. Now, one would have less transmission line problems but also less noise immunity. It seems that there must be a trade-off between the digital and analog worlds here. I grasp that more bandwidth (for faster rise times) allows faster data throughput but where is the middle ground for conveying frequency references? (i.e. at which rise time will the side-effects out weigh the benefits) Kind regards, Stephan Sandenbergh. _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
