Robert Atkinson wrote: > Hi Bruce, > It's a while since I looked at the HP circuit and patent, but if I > recall correctly a lot of the performance relied on the input circuit. > This used a line receiver with feedback. When I looked there did not > seem to be an equivalent receiver chip available. I'm aware of the sine > -square conversion thread that ran a while ago, but guess this needs as > much attention as the phase comparator. > > Robert. > Robert
Equivalent or better performance ECL line receivers are readily available but not necessary if the upper frequency limit is restricted to 20MHz or so. When HP designed this comparator performance was inadequate, this is no longer true. I have successfully used 10216 triple ECL differential line receivers in the past in constant fraction discriminators, however I would do things a little differently with more modern components. The feedback was used to implement a Schmitt trigger with about 10mV of hysteresis. This function can easily be implemented with a modern high speed comparator like an ADCMP600/601. However if you really want to push the performance envelope (and cost) by using SiGe ECL parts then using a wideband (3GHz) ECL differential line receiver is a better option. I believe that an upper frequency limit of 20MHz (compatible with high speed (> 100MHz) CMOS logic would keep the cost within bounds and satisfy most needs since one can always use a prescaler to bring the frequency down below 20MHz. The gain tempco could also easily be made very low when CMOS parts are used. The modified circuit would in fact produce 2 linear phase outputs in phase quadrature so one of the outputs is always well away from the limits of its output range where nonlinearities due to the limitation on the minimum pulse width that the exclusive OR gates can produce. Just log both outputs and sort out which to use in software when analysing the data. The quadrature outputs enable cycle slips to be unambiguously tracked and accounted for. The other option is to use more standard 3GHz ECL flipflops etc which would raise the cost somewhat but not to the levels of a full SiGe ECL implementation. Bruce _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
