From: Enrico Rubiola <[EMAIL PROTECTED]> Subject: Re: [time-nuts] Gate propagation delay jitter Date: Wed, 11 Apr 2007 00:14:01 +0200 Message-ID: <[EMAIL PROTECTED]>
Enrico, > > Then we would need to know/measure the jitter of the retiming > > flipflop. > Expected values > microwave: -120 dBrad^2/Hz flicker, -150 dB white > RF: -140 dBrad^2/Hz flicker, -150 dB white > Use a double balanced mixer, traditional configuration. > A correlation scheme is probably not necessary. So you mean I could toss in a double-balanced mixer and feed it with the sampling clock and the output lines, while feeding the flip-flop some lower clock? > On the understanding side, aliasing is the beast to kill. > A logic gate shows a gain g<>0 (analog gain!!!) during the > edges, for it behaves as a sampling system -> increased > noise bandwidth, due to aliasing. It is a sampling system. It is just that it attempts to gain out the signal to be either high or low. Wouln't meta-stability be an issue here? > William Egan wrote an illuminating article, Transact. UFFC > (1990 in my notebooks, 1992 in my memory, sorry) > > > There appears to be little definitive published data on the jitter of > > various logic gates and flipflops. > I know. Fred L. Walls did some work, proc. Freq. Control Symp, > I don't remember when. It is at times like this I am sad I don't have that access anymore. It was too much money for me at the time. Cheers, Magnus _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
