From: Enrico Rubiola <[EMAIL PROTECTED]> Subject: Re: [time-nuts] Gate propagation delay jitter Date: Wed, 11 Apr 2007 17:15:13 +0200 Message-ID: <[EMAIL PROTECTED]>
> Dear all, Hi Enrico, > I mean that the right way to reduce the jitter of a digital circuit is > to re-synchronize the output to the main clock with a D-type > flip-flop (no other types). That is natural and comes almost without saying. Assuming you have a low jitter synchronous clock to start with. > The right way to measure the jitter looks like the attached sketch. OK. > The important point is to respect the timing of the D-FF. Indeed. > There is no reason to divide the frequency. OK. > Metastability is not an issue. Not even when you have timed your D input in a particularly bad place timing- wise? My point about metastability was in interpolating counters where the coarse clock samples the signal (which can take any timing relation to the clock) and the resulting error signal will include timing variations of that DFF. The traditional trick to use two DFFs in series may be advisable unless you have secured the metastability risk by other means. > Respect the quadrature condition at the mixer inputs. > May need a buffer at the FF output > > Attached also the Egan's article. Walls, I'll search > later. OK. Thanks! Will read! Cheers, Magnus _______________________________________________ time-nuts mailing list [EMAIL PROTECTED] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
