); SAEximRunCond expanded to false Errors-To: [EMAIL PROTECTED] RETRY From: "Jack Hudler" <[EMAIL PROTECTED]> Subject: Re: [time-nuts] Timing on Ethernet Date: Fri, 3 Aug 2007 07:38:35 -0500 Message-ID: <[EMAIL PROTECTED]>
> ); SAEximRunCond expanded to false > Errors-To: [EMAIL PROTECTED] RETRY > > One thing that comes to mind, though I may be missing something here. > Ethernet is CDMA/CA; would you not loose phase lock during a collision > because of a corrupted carrier? As he was considering 10Base-T or 100Base-T there is not real collisions on the cable as on the old coax days. Ethernet has evolved from those days while attempting to retain the simplicity. The result is not magnificent but working OK enought for most cases. A good trick is to measure the phase of the carrier just at the last edge of the preamble, since that is where the static preamble pattern creates a static ISI so very little of the forgoing data affects the phase of the clock. This trick is used in other cable techniqures. If running a "hacked" variant of 10Base-T or 100Base-T one could fairly well optimize things for improved performance. For a facility like CERN, I think that normal cabel assymetries will be sufficiently low such that they would not require explicit handling, unless you have higher synchronisation demands, but in that case I would strongly suggest a different solution. Looking at the IEEE 1588 while implementing in your own FPGA seems like an odd choice. It is an option, but you could fairly easy cook up something which fits your needs. It is not too hard actually. The most important issue is what kind of performance do you need? Maximum time-errors? Stability requirements? Full UTC time or only UTC coordinated PPS? 10 MHz clock? There are several ways to "hack" Ethernet with diffrenent benefits. Cheers, Magnus _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
