); SAEximRunCond expanded to false Errors-To: [EMAIL PROTECTED] RETRY
> -----Original Message----- > From: Magnus Danielson [mailto:[EMAIL PROTECTED] > Sent: Monday, August 06, 2007 8:49 PM > To: Pablo Alvarez Sanchez > Cc: [email protected] > Subject: Re: [time-nuts] PLL on FPGA > > From: "Pablo Alvarez Sanchez" <[EMAIL PROTECTED]> > Subject: RE: [time-nuts] PLL on FPGA > Date: Mon, 6 Aug 2007 18:49:23 +0200 > Message-ID: > <[EMAIL PROTECTED]> > > Is your sample/message rate that of 8 kHz? My sampling rate is not constant. I wait until I detect a 3 ticks of the 500kHz clock and then start sampling. After 2048 samples I do an average (first order CIC) and pass this value to the PI. The PI operates at variable ratio of ~250Hz if there are no data or 125Hz if there are data. The fact of not having a regular trafic on the cable may also affect a bit to the final performance. > > > > The jitter I measured with a good scope is ~120ps between > > > two modules > > > > for several minutes. > > > > > > Peak-to-Peak or RMS? For pure noise measures only use RMS > values!!! > > > > > > This is RMS > It is high then. You should be able to get better performance. > Thanks for the info. This is really what I wanted to know. I will work on this point. What do you think I should be able to obtain? Do you think a bang-bang phase detector and setting a good reference point should do a better job? > Cheers, > Magnus > Cheers Pablo _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
