At 06:02 AM 11/27/2007, you wrote: >You will need a clock shaper to convert the sine to a digital signal, and >a series of dividers. > >You can look at my page on clock shapers for ideas: > >http://www.ko4bb.com/Timing/ClockShaper.html > >If you look through the archives, I believe earlier this year there was a >thread about the respective noise performance of various logic >technologies, but I am sure someone can recommend the current >best-in-class divider for low noise. For any but the most demanding >applications, I am sure that standard CMOS decade counters in the AC, HC, >ACT or HCT series would work fine, such as the 74ACT162.
While designing a timing distribution system at a cyclotron facility that required stability and low jitter (in the low picoseconds), I found that thermal changes caused the logic thresholds to vary which caused the edges to drift dozens of picoseconds. The solution was, whenever possible, to use differential logic signals. I was using the ECLips ECL logic family so that was an easy fix. Resync'ing to the input clock should be done as required and again close to the output. -Mike- _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
