> That is good information. My other fear is that the user's 10 MHz > will pick up some 60 Hz on the way to my system, but I suppose there > is no way I want to be narrower than 60 Hz on my loop bandwidth. >
Yeah, not without a much-better OCXO than that. Of course, if your other system constraints are such that the VCXO's noise is not important, it won't pay to discipline it in a wideband loop. If you don't need the cleanup effect, a narrowband loop is preferable for just that reason (spur suppression). > > Do not use a 50K resistor at your charge-pump output, though! That will > > cause the PLL to 'hunt' continually, adding reference sidebands to the > > output. I would use a JFET or CMOS analog switch, or even a relay, to > > disconnect the charge pump and switch in the half-rail fixed supply. > > That is what I was afraid of. Thanks for the warning. You could always try it and see what happens, but at least in an ordinary RF PLL, you'd ordinarily go out of your way to avoid sourcing or sinking current from the charge pump. Your reference frequency is very far from the loop bandwidth in this case (10 MHz versus ~1 kHz), so you might get away with the resistive-divider idea. It wouldn't be the best practice in the general case, though. (I wouldn't worry about resistor noise either way, because the VCXO's tuning sensitivity isn't very high.) -- john, KE5FX _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
