There was a thread some time ago just about that. It was probably 2007, so if you look in the archives, you should find it.
I will look for it too, as I want to index it for future reference, and if I find it first, I'll post it again. Didier > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf Of Anders Time > Sent: Friday, January 25, 2008 7:02 AM > To: time-nuts@febo.com > Subject: [time-nuts] Low phase noise digital divider (in > 600MHz to10MHz area) > > Have been locking around for a good article on how to design > a good Low phase noise digital divider(in 600MHz to 10MHz > area), but the have not found any good literature. Today most > people talk about regenerative dividers, but are a rather > complex subject. > Does anyone have experience in what logic family that have > the lowest noise TTL, AC, HC, F etc? > What is the upper limit for ECL diviers? My first idea was to > use ECL to divide down to 100MHz area and then to use lower > noise TTL to go down to 10MHz. > What about edge-conditioning circuit at divider input? Have > seen people talk about it, but no info what it does? > Thanks > Anders No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.5.516 / Virus Database: 269.19.11/1242 - Release Date: 1/24/2008 8:32 PM _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.