Hello Tom, Bruce mentioned there is a validity bit that can be checked for holdover. I wonder if a small micro can be used to hold the EFC voltage steady without much effort. Or maybe using Super-Caps in the loop filter? Or maybe use one of those new 24 bit Sigma-Delta ADC/DAC chips to capture a 24 bit word (ADC) and feed that to the 24 bit DAC during holdover. Kind of a 24 bit high-precision sample-and-hold circuit. It would be a shame to have such a good OCXO performance go unused during short hold-overs. Interesting technical challenge. bye, Said In a message dated 2/13/2008 11:54:08 Pacific Standard Time, [EMAIL PROTECTED] writes:
The Miller design doesn't support holdover. You can either run it free (using JP1, see earlier mail) or run it GPS-locked. I think the PLL is all of one gate and an RC filter so there's nothing to "hold" the EFC. See his web site for details. **************The year's hottest artists on the red carpet at the Grammy Awards. Go to AOL Music. (http://music.aol.com/grammys?NCID=aolcmp00300000002565) _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
