John,
You may want to try the CPLD divider code I sent you many moons ago. It'll divide 5MHz down to 1PPS with no problem at all. The output jitter ought to be decent and easy to calculate. I often use that code on a Reflock II board, because it has a nice HF input conditioner in addition to power regs and JTAG connector. Reflock II is not bad, but I am sure we could spin a board that work even better for general time-nut nuttiness(*) without a lot of difficulty. Assuming of course there was sufficient interest . -ch (*)I would prefer Xilinx but I can live with Altera. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
