[EMAIL PROTECTED] wrote: > Hi David, > > It looks like your design is pretty far along, so maybe it's too late for > this suggestion, but one thing you might consider is replacing the 7400 > series logic with a 5V CPLD programmable logic device. > > This could offer several advantages: > > 1) any issues (such as jitter) could be addressed by reflashing the CPLD and > may let you avoid hardware PCB changes. > You cannot "fix" modulation of the higher frequency divider outputs by lower frequency outputs by reprogramming a CPLD or FPGA. External reclocking/resynchronising flipflops (one per output frequency) are required > 2) new features or applications (specially created triggers or unusual pulse > outputs) that may come up in the future could possibly be added, again > without PCB changes. > > 3) a full simulation of the design could performed prior to construction > > Xilinx offers a free (as in free beer, not as in free speech) complete > programmable logic design simulation and synthesis tool for download from > their website. It's called ISE WebPACK. There's a version for windows or > linux host: > > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > This tool is quite an amazing free download. I had to go through a few > gyrations to get the USB "cable", as they call the downloader, to build for > linux: > > http://wiki.archlinux.org/index.php/Xilinx_ISE_WebPACK_10.1_wUSB_cable_on_ArchLinux-2.6.24 > > But I'm sure it's easier on windows. > > The CPLD's (unlike the FPGAs) are single chip solutions. The XC9500 family is > 5V logic compatible and could fit into something as small as a 44 pin package. > > The ISE design tool offers built in Verilog, VHDL or CUPL programming > laguages, or (and this really amazed me) a built in schematic editor tool! > This lets you capture the design, just as you have, in a schematic, and then > synthesize the logic and perform a complete simulation of your captured > schematic. > > You could even just download the tool, capture your existing schematic (there > are logic elements for 7400 series logic devices) and use the tool as a > simulation engine to test your design. Even if you ultimately plan to use the > 7400 parts. > > Just dont use this method to implement the dividers etc in the CPLD. Its better to use a fully synchronous decade divider chain if possible as this eliminates all the realignment logic required with ripple clocked divider chains.
Another issue with some (but not all) CPLDs are the power supply requirements, at least with CMOS the divider (when not driving too many outputs) has a low power supply current making battery operation feasible. > No, I don't work for Xilinx 8-) but I did just finish a design using this > tool and was suitably impressed. While I write quite a bit of code in my day > to day work, I hadn't designed programmable logic since the old PAL days (way > back in the early 80's 8-) I used the schematic capture feature of ISE to > input the design and then found my way into writing the control state > machines in verilog. Then simulated the functionality and when we built the > hardware the whole thing just worked, right out of the box! > > (The design ran an A/D converter, captured the results into a static ram, and > then allowed SPI access to the ram from an AVR microcontroller) > > I know going to programmable logic can seem like a big unknown, but perhaps > it's worth just downloading the tool and checking it out. > > The CPLD wouldn't replace any of your signal conditioning, fusing, etc, but > it could replace the core counters, muxes, etc and give you something that > could continue to grow as the years go by. > > Very Cool Project! > > johnea > Bruce _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
