What Rick says is completely correct. I took the general approach (so you can generate any frequency) and by using a binary counting scheme, the number of clock cycles required is reduced to 9 (for 24-bit) or 10 (for 32-bit), provided you use an AVR processor.
The advantage then is that you have a high sample rate (1.111MHz or 1MHz with a 10MHz clock) and can generate frequencies up to about 300kHz from 10MHz. The difficulty with adding a preset value at overflow is that first you have to test for overflow, and second that the time around the loop is changed by the instructions involved in loading. It's no problem at all in this particular application, but in the general case as a high frequency signal generator this introduces undesirable jitter. You could of course run the whole shebang in an interrupt and thus avoid the jitter, replacing it instead with interrupt latency jitter. This you can avoid by putting the micro to sleep after each interrupt, so the interrupt routine always starts the same way. There's an even better really simple trick. If you use a GPSDO as the source of 10MHz, use a simple 24-bit binary DDS to generate close to 32768Hz, and then use the 1pps output from the GPSDO to drive an interrupt to reset the phase. You need only do it every few hundred seconds, easy to set up in the micro. I use this technique to generate GPS synchronous radio transmissions on LF. 73, Murray _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
