The D flipflop phase detector where the clock input is driven by the PPS output of a GPS timing receiver, the D input is driven by the OCXO frequency (or a subharmonic thereof), and the filtered Q output is sampled after a sufficient delay to reduce the probability of a metastable output to an insignificant level and used (after filtering) to drive the EFC input of the OCXO to be disciplined can be viewed as akin to a sigma delta loop operating in the phase domain. The intrinsic noise and or quasi sawtooth jitter of the PPS output serve to break up idle tones that may otherwise be present. For correct operation the period of the D input frequency should be greater than the PPS sawtooth dither or intrinsic PPS jitter.
The loop will inherently lock the frequency at the D flipflop input to a harmonic of 1Hz, so to ensure the OCXO locks to the desired frequency either the tuning range must be restricted or the OCXO frequency be divided down to a suitable frequency that precludes the OCXO locking to the wrong harmonic. If hardware sawtooth correction is used on an M12M timing receiver the residual PPS jitter drops to a few nanosec and the effective resolution of the D flipflop phase detector adapts to a fraction of that. Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
