Why not add a hardware latch with a fixed delay to read. That is the delay 
controls the latch function after the counter is static as well as the 
interrupt. Then reset the latch buffer on the last read. We have a fixed 
hardware delay plus a software delay to allow for but eliminate some of the 
variability. And reduce the failed read due to software delay. Now a second 
interrupt / read will indicate delays greater than the tick rate if our OS has 
interrupts that are off greater than the tick rate minus the delay of the 
latch. Our choice would be to slow the tick rate or reduce the interrupts off 
blind time if we have many failed reads where the tick is more than one. The 
idea would be to reduce the error to a rare event. This problem is like the 
meta stable problem discussed here before so perhaps the fixes are the same.

Stanley 



----- Original Message ----
From: "Lux, James P" <[email protected]>
To: Discussion of precise time and frequency measurement <[email protected]>
Sent: Sunday, May 17, 2009 9:19:50 AM
Subject: Re: [time-nuts] FreeBSD, NetBSD, or Minix-III?




On 5/16/09 10:00 PM, "Poul-Henning Kamp" <[email protected]> wrote:

> In message <[email protected]>, Hal
> Murr
> ay writes:
> 
>> This is one of the reasons why I was looking for a low-cost FPGA on PCI board
>> with some way to get a couple of external inputs.
>> 
>> Things get interesting if your hardware splits a 64 bit read into 2 32 bit
>> transfers.  Many years ago, all Intel chips did that.  I don't know about
>> today.
> 
> You don't need a 64bit counter in the first place.

You might want a 64 bit counter, if you want to keep time across processor
resets.

In which case, if you're saddled with 32 bit (or 8 bit!) reads, you have to
do multiple reads, so that by the end of the process, you can assure
yourself it's consistent.

E.g read high, read low, read high, read low
So you can check low #1 against low #2, and figure out if you had a roll
over.



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