>> I would use a DDS, but only for fine tuning
>> in a summing loop. E.g., use a
>> DAC to pretune the varactor or YTO to
>> within 50 or so MHz, feed the sampler
>> LO port with a clean 100 MHz crystal,
>> then close the loop by comparing the
>> sampler IF to the DDS-generated offset signal.
>
> This is a nice technique. The trick is in making sure you
> lock to the right comb and the right side..
Jim, I had no problems doing that on my old design
LO was a bit higher in frequency making it easier
and yes the harmonic mixer was driven with 18-20dBm
OK as it is not a power critical application.
And on top of that the micro-controller driving that
had a self calibration routine that scanned through
stepping 50MHz and adjusting DAC for a zero PFD output
then store on a table, that on normal use the uC interpolates
within each 50MHz tabled point to get the right DAC value.
(uC times are not to be considered here as all calculations
are done much before during the so called setup time)
So cleverness on board (i.e. microprocessor and
soft) is not a problem for the application.
My issue is RF and microwave simplicity ;-)
tks for your good comments and articles.
Luis Cupido.
ct1dmk
Lux, Jim (337C) wrote:
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf
Of John Miles
Sent: Wednesday, October 14, 2009 4:44 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] fast freq. synthesis schemes
Pretuning is the right strategy, but for microsecond agility, YIGs may be
the wrong choice due to their main-coil inductance.
If I were building an agile 12-18 GHz synthesizer I'd try a heterodyne
scheme with varactor-tuned oscillators and a fixed (or very coarsely tuned)
YIG or DRO. Either way, you would probably use a sampler, such as the parts
in the Aeroflex/Metelics catalog, to construct the outermost PLL. Suitable
counter and PFD chips exist as well (Hittite etc.) but samplers are cheaper
and easier to use if you don't mind designing the IF circuitry for them.
Ooohh.. Sampling Phase Detectors or Harmonic Mixers.. The problem is that you
have to hit them with a lot of power on the reference port (+20dBm wouldn't be
unusual) Depending on your application, making that much LO power that is
suitably quiet is a challenge. Presumably, though, you're not DC power
limited, so that helps.
Getting a PLL with simple single integer N is pretty easy with the Hittite
parts, especially if you can tolerate N that is a multiple of 4 or 8. There's
a paper out there by S.K.Smith, et al., that describes a breadboard PLL we did
at 8GHz, where we drove the reference input with the output of a DDS mixed with
a fixed signal.
http://tmo.jpl.nasa.gov/progress_report/42-166/166A.pdf
take a look at Figure 6 and 7
However, that won't change in less than a microsecond (the loop bandwidth is
too narrow).. you could widen up the loop bandwidth, but the reference source
would need to be quieter (not a challenge.. we didn't take any special efforts
to make our DDS quiet, etc.)
The earlier paper by Cook, et al.,
http://tmo.jpl.nasa.gov/progress_report/42-156/156C.pdf
shows a more traditional SPD DRO PLL, and gives some performance analysis of
the loop. Just as in the Smith paper, tuning speed wasn't a big deal for us,
but the theory is there to generalize it.
I would use a DDS, but only for fine tuning in a summing loop. E.g., use a
DAC to pretune the varactor or YTO to within 50 or so MHz, feed the sampler
LO port with a clean 100 MHz crystal, then close the loop by comparing the
sampler IF to the DDS-generated offset signal.
This is a nice technique. The trick is in making sure you lock to the right
comb and the right side.. But the external DAC can help with that.
That way the PN is dominated
by the lower N factor assocaited with the 100 MHz comb, and the resolution
is determined by the DDS.
Yes.
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