On 02/03/2010 07:59 PM, Matt Ettus wrote:
Does anyone have any experience using CPLDs for very low phase noise dividers? You can get an XC9536XL from Xilinx for around $1, and I thought it would make a good divide by 2 through 10 device.
9500XL (3.3V) is, I believe, similar to 9500 (5V). A downside to the way the 9500 is built is the rather high static power consumption, and that the static current consumption is dependent on the internal state of the signals. If you have a single divider in a part it is not a problem. But if you divide by 2 and 10, the '2' output will be modulated by the divide-by-10 in ways one may not expect since the input threshold of the clock signal changes.
An alternative I like better is XCR3032XL, which is entirely CMOS. No current-source-driven AND/OR, with a static current consumption that isn't dependent on the internal state. Thus, the internal state does not move the threshold of the global clock around.
Output slew rate is faster than 1ns when driving into 150 ohm. /Kasper Pedersen _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
