From: "Garry Thorp" <[email protected]>
Subject: Re: [time-nuts] Advice on 10 MHz isolation/distribution /
Phase Noise of 74AC gates
The attached plot shows the 12.5MHz phase noise plus that of the 100MHz
OCXO. The divider phase noise tracks 18dB below the OCXO at low offsets
as expected, before its flicker noise and eventual noise floor
predominate. I was primarily interested in seeing what the flicker noise
was like, but I was surprised when I saw how low the floor was!
The E5052B does the necessary calibration automatically before doing a
measurement - from my experience with the instrument I have no reason to
doubt the validity of the result. (The indicated 100MHz phase noise in
the ~1-50kHz region is actually limited by the E5052B, owing to my
setting only 100 correlations. However it shows it low enough to
indicate that the CMOS noise dominates over that range.)
I realise that a divider is very different from a simple inverter, but I
think this gives an useful indication of what AC logic is capable of.
Garry
Pascall Electronics Ltd - Registered in England No: 1316674 VAT Registration
No: GB 448705134 Registered Office: Brunswick Road, Cobbs Wood, Ashford, Kent,
TN23 1EH
Gary,
Hi Gary,
Interesting plot, thanks for sharing. Like I said previously; logic gates
absolutely have their uses in reference buffering. I have used them before,
and will continue to do so.
However, I think in the most demanding applications the relatively-poor 1/F
noise of CMOS loses out to bipolar transistors. If one wanted to stick with a
square wave reference, or implement a digital phase detector or divider other
types of logic like ECL are more appropriate. Also, digital logic, even
high-current ECL, is more susceptible to AM to PM conversion from power supply
noise.
It all depends on what you need to do. CMOS is pretty good, but can't get you
that last bit of performance especially close in. Which is, after all, what a
clean reference is for.
Clay
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